-
1
-
-
0030403625
-
Noise in deep submicron digital design
-
K. L. Shepard and V. Narayanan. Noise in deep submicron digital design. In Proc. ICCAD, pages 524-531, 1996.
-
(1996)
Proc. ICCAD
, pp. 524-531
-
-
Shepard, K.L.1
Narayanan, V.2
-
2
-
-
77950983488
-
Globalharmony: Coupled noise analysis for full-chip re interconnect networks
-
K. L. Shepard, V. Narayanan, P. C. Elmendorf, and G. Zheng. Globalharmony: Coupled noise analysis for full-chip re interconnect networks. In Proc. ICCAD, page 139146, 1997.
-
(1997)
Proc. ICCAD
, pp. 139146
-
-
Shepard, K.L.1
Narayanan, V.2
Elmendorf, P.C.3
Zheng, G.4
-
4
-
-
34247502116
-
Predictive technology model for nano-cmos design exploration
-
W. Zhao and Y. Cao. Predictive technology model for nano-cmos design exploration. In Trans. J. Emerg. Technol. Comput. Syst., volume 3, 2007.
-
(2007)
Trans. J. Emerg. Technol. Comput. Syst.
, vol.3
-
-
Zhao, W.1
Cao, Y.2
-
5
-
-
34748898842
-
Mapping statistical process variations toward circuit performance variability: An analytical modeling approach
-
Oct.
-
Y. Cao and. L. T. Clark. Mapping statistical process variations toward circuit performance variability: An analytical modeling approach. In IEEE Trans, on CAD, volume 26, pages 1866-1873, Oct. 2007.
-
(2007)
IEEE Trans, on CAD
, vol.26
, pp. 1866-1873
-
-
Cao, Y.1
Clark, L.T.2
-
6
-
-
0033699258
-
Impact of in-terconnect variations on the clock skew of a gigahertz microprocessor
-
Y. Liu, S. R. Nassif, Larry Pileggi, and A. J. Strojwas. Impact of in-terconnect variations on the clock skew of a gigahertz microprocessor. In Proc. DAC, pages 168-171, 2000.
-
(2000)
Proc. DAC
, pp. 168-171
-
-
Liu, Y.1
Nassif, S.R.2
Pileggi, L.3
Strojwas, A.J.4
-
7
-
-
34547155744
-
Computation of accurate interconnect process parameter values for performance corners under process variations
-
F. Huebbers, A. Dasdan, and Y. Ismail. Computation of accurate interconnect process parameter values for performance corners under process variations. In Proc. DAC, pages 797-800, 2006.
-
(2006)
Proc. DAC
, pp. 797-800
-
-
Huebbers, F.1
Dasdan, A.2
Ismail, Y.3
-
8
-
-
50249112738
-
Multi-layer interconnect performance corners for variation-aware timing analysis
-
F. Huebbers, A. Dasdan, and Y. Ismail. Multi-layer interconnect performance corners for variation-aware timing analysis. In Proc. ICCAD, pages 713-718, 2007.
-
(2007)
Proc. ICCAD
, pp. 713-718
-
-
Huebbers, F.1
Dasdan, A.2
Ismail, Y.3
-
9
-
-
34748903606
-
Worst-case delay analysis considering the variability of transistors and interconnects
-
T. Fukuoka, A. Tsuchiya, and H. Onodera. Worst-case delay analysis considering the variability of transistors and interconnects. In Proc. ISPD, pages 35-42, 2007.
-
(2007)
Proc. ISPD
, pp. 35-42
-
-
Fukuoka, T.1
Tsuchiya, A.2
Onodera, H.3
-
11
-
-
4444343172
-
Variational delay metrics for interconnect timing analysis
-
K. Agarwal, D. Sylvester, D. Blaauw, F. Liu, S. Nassif, and S. Vrudhula. Variational delay metrics for interconnect timing analysis. In Proc. DAC, pages 381-384, 2004.
-
(2004)
Proc. DAC
, pp. 381-384
-
-
Agarwal, K.1
Sylvester, D.2
Blaauw, D.3
Liu, F.4
Nassif, S.5
Vrudhula, S.6
-
12
-
-
33845624686
-
Statistical timing analysis with coupling
-
D. Sinha and H. Zhou. Statistical timing analysis with coupling. In IEEE Trans, on. CAD, pages 524-531, 2006.
-
(2006)
IEEE Trans, On. CAD
, pp. 524-531
-
-
Sinha, D.1
Zhou, H.2
-
13
-
-
0020778211
-
Signal delay in re tree networks
-
July
-
J. Rubinstein, P. Penfield, and M. A. Horowitz. Signal delay in re tree networks. In IEEE Trans, on CAD. volume 2, pages 202-211, July 1983.
-
(1983)
IEEE Trans, on CAD
, vol.2
, pp. 202-211
-
-
Rubinstein, J.1
Penfield, P.2
Horowitz, M.A.3
-
14
-
-
2442520192
-
Gate delay calculation considering the crosstalk capacitances
-
S. Abbaspour and M. Pedram. Gate delay calculation considering the crosstalk capacitances. In Proc ASP-DAC, pages 852-857, 2004.
-
(2004)
Proc ASP-DAC
, pp. 852-857
-
-
Abbaspour, S.1
Pedram, M.2
-
15
-
-
0034483941
-
Miller factor for gate-level coupling delay calculation
-
P. Chen, D. A. Kirkpatrick, and K. Keutzer. Miller factor for gate-level coupling delay calculation. In Proc ICCAD, pages 68-75, 2000.
-
(2000)
Proc ICCAD
, pp. 68-75
-
-
Chen, P.1
Kirkpatrick, D.A.2
Keutzer, K.3
-
16
-
-
0033873392
-
Modeling of interconnect capac-itance, delay, and crosstalk in vlsi
-
S. C. Wong, G. Y. Lee, and D. J. Ma. Modeling of interconnect capac-itance, delay, and crosstalk in vlsi. In IEEE Trans, on Semiconductor Manufacturing, volume 13, pages 108-111, 2000.
-
(2000)
IEEE Trans, on Semiconductor Manufacturing
, vol.13
, pp. 108-111
-
-
Wong, S.C.1
Lee, G.Y.2
Ma, D.J.3
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