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Volumn , Issue , 2004, Pages 853-858

Gate delay calculation considering the crosstalk capacitances

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; GATE DELAY; INTERCONNECT COUPLING; THRESHOLDS METHOD;

EID: 2442520192     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (23)
  • 1
    • 34748823693 scopus 로고
    • The transient response of damped linear networks with particular regard to wideband amplifiers
    • Jan.
    • W. C. Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers," Journal of Applied Physics, 19, Jan. 1948, pp. 55-63.
    • (1948) Journal of Applied Physics , vol.19 , pp. 55-63
    • Elmore, W.C.1
  • 3
    • 0024906813 scopus 로고
    • Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation
    • P. R. O'Brien and T. L. Savarino, "Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation," Proc. of IEEE Int'l Conf. on Computer Aided Design, 1989, pp. 512-515.
    • (1989) Proc. of IEEE Int'l Conf. on Computer Aided Design , pp. 512-515
    • O'Brien, P.R.1    Savarino, T.L.2
  • 12
    • 0031631926 scopus 로고    scopus 로고
    • A new algorithm for computing the "effective capacitance" in deep sub-micron circuits
    • June
    • R. Macys, S. McCormick, "A New Algorithm for Computing the "Effective Capacitance" in Deep Sub-micron Circuits," Proc. of IEEE Custom Integrated Circuits Conference, June 1998, pp. 313-316.
    • (1998) Proc. of IEEE Custom Integrated Circuits Conference , pp. 313-316
    • Macys, R.1    McCormick, S.2
  • 13
    • 0032715195 scopus 로고    scopus 로고
    • Improved effective capacitance computations for use in logic and layout optimization
    • A. B. Kahng and S. Muddu,' "Improved Effective Capacitance Computations for Use in Logic and Layout Optimization." Proc. of the 12th International Conference on VLSI Design, 1999, Pages: 578-582.
    • (1999) Proc. of the 12th International Conference on VLSI Design , pp. 578-582
    • Kahng, A.B.1    Muddu, S.2
  • 14
    • 0030141612 scopus 로고    scopus 로고
    • Performance computation for pre-characterized CMOS gates with RC loads
    • May
    • F. Dartu, N. Menzes, and L.T. Pileggi," Performance computation for pre-characterized CMOS gates with RC loads," IEEE Transaction on CAD, vol. 15, pp. 544-553, May 1996
    • (1996) IEEE Transaction on CAD , vol.15 , pp. 544-553
    • Dartu, F.1    Menzes, N.2    Pileggi, L.T.3
  • 15
    • 0030686019 scopus 로고    scopus 로고
    • Calculating worst-case gate delays due to dominant capacitance coupling
    • June
    • F. Dartu, L.T. Pileggi, "Calculating worst-case gate delays due to dominant capacitance coupling," Proc. Of Design Automation Conference, pp 46-51, June 1997
    • (1997) Proc. Of Design Automation Conference , pp. 46-51
    • Dartu, F.1    Pileggi, L.T.2
  • 20
    • 79955052276 scopus 로고    scopus 로고
    • Fast and accurate wire delay estimation for physical synthesis of large ASICs
    • R.Puri, D.S. Kung, A.D. Drumm, "Fast and Accurate Wire Delay Estimation for Physical Synthesis of Large ASICs," Proc. of GLSVLSI, 2002
    • (2002) Proc. of GLSVLSI
    • Puri, R.1    Kung, D.S.2    Drumm, A.D.3
  • 21
    • 0034483941 scopus 로고    scopus 로고
    • Miller factor for gate-level coupling delay calculation
    • P. Chen, D.A. Kirkpatrick, K. Keutzer, "Miller Factor for Gate-Level Coupling Delay Calculation", Proc. of ICCAD, pp 68-74, 2000
    • (2000) Proc. of ICCAD , pp. 68-74
    • Chen, P.1    Kirkpatrick, D.A.2    Keutzer, K.3
  • 23
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    • http://mathworld.wolfram.com


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.