Multi-layer interconnect performance corners for variation-aware timing analysis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 713-718

  Huebbers, Frank ^a   Dasdan, Ali ^b   Ismail, Yehea ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

^b YAHOO INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER-AIDED DESIGN; EXHAUSTIVE SEARCH; EXPONENTIAL COMPLEXITY; INTERCONNECT PERFORMANCE; INTERNATIONAL CONFERENCES; MULTI LAYERING; PROCESS VARIATIONS; SEARCH METHODS; SIMULATION-BASED; SIMULATION-BASED METHOD; SPICE SIMULATIONS; STAGE DELAY; TIMING ANALYSIS;

CHANNEL CAPACITY; CHLORINE COMPOUNDS; DESIGN; STAGES;

ERRORS;

EID: 50249112738     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397349     Document Type: Conference Paper

References (21)

1. M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits," in Proc. of ICCAD. 2000, pp. 62-67.
2. Y. Liu, S. R. Nassif, L. T. Pillegi, and A. J. Strojwas, "Impact of interconnect variations on the clock skew of a gigahertz microprocessor," in Proc. of DAC. 2000, pp. 168-171.
3. O. S. Nakagawa, N. Chang, S. Lin, and D. Sylvester, "Circuit impact on skew-comer analysis of stochastic process variation in global interconnect," in UTC, 1999, pp. 230-232.
4. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture," in Proc. of DAC, 2003, pp. 338-342.
5. S. R. Nassif, "Modeling and analysis of manufacturing variations," in Proc. of CICC, 2001, pp. 223-228.
6. J. Luo, S. Sinha, Q. Su, J. Kawa, and C. Chiang, "An IC manufacturing yield model considering intra-die variations," in Proc. of DAC, 2006, pp. 749-754.
7. K. Yamada and N. Oda, "Statistical corner conditions of interconnect delay (corner LPE specifications)," in Proc. of ASP-DAC, 2006, pp. 706-711.
8. P. S. Zuchowski, P. A. Habitz, J. D. Hayes, and J. H. Oppold, "Process and environmental variation impacts on ASIC timing," in Proc. of ICCAD, 2004, pp. 336-342.
9. F. Huebbers, A. Dasdan, and Y. Y. Ismail, "Computation of accurate interconnect process parameter values for performance corners," in Proc. of DAC, 2006, pp. 797-800.
10. T. Fukuoka, A. Tsuchiya, and H. Onodera, "Worst-case delay analysis considering the variability of transistors and interconnects," in Proc. of ISPD, 2007, pp. 35-41.
11. Nanoscale Integration and Modeling (NIMO) Group, "Predictive technology modeling (PTM)," http://www.eas.asu.edu/~ptm. 2006.
12. N. S. Nagaraj, T. Bonifield, A. Sing, F. Cano, U. Narasimha, M. Kukarni, P. Balsara, and C. Cantrell, "Benchmarks for interconnect parasitic resistance and capacitance," in Proc. of ISQED, 2003, pp. 163-168.
13. S.-C. Wong, G.-Y. Lee, and D.-J. Ma, "Modeling of interconnect capacitance, delay, and crosstalk in VLSI," IEEE Trans. on Semicon. Manuf. vol. 13, no. 1, pp. 108-111, 2000.
14. W. Elmore, "The transient response of damped linear networks with particular regard to wideband amplifiers," J. of Applied Physics, vol. 19, no. 1, pp. 55-63, 1948.
15. K. D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins, "Fidelity and near-optimality of Elmore-based routing constructions," in Proc. of ICCD, 1993, pp. 81-84.
16. J. Cong, L. He, C-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," in Integration, the VLSI J., vol. 21, 1996, pp. 1-94.
17. C. Alpert and A. Devgan, "Wire segmenting for improved buffer insertion," in Proc. of DAC. 1997, pp. 588-593.
18. M. Ketkar, K. Kasamsetty, and S. S. Sapatnekar, "Convex delay models for transistor sizing," in Proc. of DAC. 2000, pp. 655-660.
19. P. K. Sancheti and S. S. Sapatnekar, "Interconnect design using convex optimization," in Proc. of CICC. 1994, pp. 549-552.
20. J. Nocedal and S. Wright, Numerical Optimization, 2nd ed. Springer. 2006.
21. T. Sakurai and A. R. Newton, "Alpha-power law mosfet model and its application to cmos inverter delay and other formulas," JSSC, vol. 25, no. 2, pp. 584-594. 1990.