Worst-case delay analysis considering the variability of transistors and interconnects

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2007, Pages 35-42

  Fukuoka, Takayuki ^a   Tsuchiya, Akira ^a   Onodera, Hidetoshi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

Interconnect; Process variation; Worst case delay

Indexed keywords

OPTICAL INTERCONNECTS; PARAMETER ESTIMATION; STATISTICAL METHODS; THICKNESS MEASUREMENT;

DRIVE STRENGTH; INTERCONNECT LENGTH; PROCESS VARIATION; WORST-CASE DELAY;

TRANSISTORS;

EID: 34748903606     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1231996.1232006     Document Type: Conference Paper

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