An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 6, 2008, Pages 1430-1440

  Jiang, Shan ^a,b   Do, Manh Anh ^a   Yeo, Kiat Seng ^a   Lim, Wei Meng ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b Indira Gandhi Centre for Atomic Research   (India)

Author keywords

Analog to digital converters (ADCs); Digital receiver; High speed; Operational amplifier (opamp); Pipelined ADCs; Sample and hold (S H)

Indexed keywords

OPERATIONAL AMPLIFIERS; PIPELINES; SIGNAL SAMPLING; SIGNAL TO NOISE RATIO; TIMING CIRCUITS;

ANALOG TO DIGITAL CONVERTERS; DIGITAL RECEIVERS; HIGH SPEED; OPERATIONAL AMPLIFIER (OPAMP); PIPELINED ADCS; SAMPLE-AND-HOLD;

ANALOG TO DIGITAL CONVERSION;

EID: 53849119164     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.916613     Document Type: Article

References (28)

1. J. M. Wilson, "The next generation of wireless LAN emerges with 802. 11n," Technol. Intel Mag., pp. 1-8, Aug. 2004.
2. S. Limotyrakis, S. D. Kulchycki, D. K. Su, and B. A. Wooley, "A 150-MS/s 8-bit 71-mW CMOS time-interleaved ADC," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1057-1067, May 2005.
3. J. Huang and R. R. Spencer, "The design of analog front ends for 1000BASE-T receivers," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 10, pp. 675-684, Oct. 2003.
4. "Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications High-Speed Physical Layer in the 5 GHz Band," Sep. 1999.
5. "Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band," Jun. 2003.
6. T. H. Meng, B. McFarland, D. Su, and J. Thomson, "Design and implementation of an all-CMOS 802.11a wireless LAN chipset," IEEE Commun. Mag., pp. 160-168, Aug. 2003.
7. M. Zargari, M. Terrovitis, S. H.-M. Jen, B. J. Kaczynski, D. K. Su, and B. A. Wooley, "A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2239-2249, Dec. 2004.
8. S. S. Mehta, D. Weber, M. Terrovitis, K. Onodera, T. H. Meng, and B. A. Wooley, "An 802.11g WLAN SoC," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2483-2491, Dec. 2004.
9. S. Khorram, H. Darabi, Z. Zhou, Q. Li, T. F. J. Trachewsky, and A. Rofougaran, "A fully integrated SoC for 802.11b in 0.18- μm CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2492-2501, Dec. 2005.
10. J. Arias, V. Boccuzzi, L. Quintanilla, L. Enríquez, D. Bisbal, M. Banu, and J. Barbolla, "Low-power pipeline ADC for wireless LANs," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1338-1340, Aug. 2004.
11. J. Li and U.-K. Moon, "A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1468-1476, Sep. 2004.
12. I. Ahmed and D. A. Johns, "A 50-MS/s (35 mW) to 1-KS/s (15 μW) power scaleable 10-bit pipelined ADC using rapid power-in opamps and minimal bias current variation," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2446-2455, Dec. 2005.
13. B. Xia, A. V. Garcia, and E. S. Sinencio, "A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/ bluetooth receiver," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 530-539, Mar. 2006.
14. W. Kester, Data Conversion Handbook. Amsterdam, The Netherlands: Elsevier, 2005.
15. I. Mehr and L. Singer, "A 55-mW, 10-bit, 40-Msample/s nyquist-rate CMOSADC," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 318-325, Mar. 2000.
16. K. Lee and R. G. Meyer, "Low-distortion switched-capacitor filter design techniques," IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1103-1113, Dec. 1985.
17. W. M. Sansen, H. Qiuting, and K. A. I. Halonen, "Transient analysis of charge transfer in SC filters-gain error and distortion," IEEE J. Solid-State Circuits, vol. SC-22, no. 2, pp. 268-276, Apr. 1987.
18. S. Jiang, M. A. Do, and K. S. Yeo, "A 200-MHz CMOS mixed-mode sample-and-hold circuit for pipelined ADCs," in Proc. IFIP Int. Conf. Very Large-Scale Integr., Nice, France, Oct. 2006, pp. 352-365.
19. S. H. Lewis, "Optimizing the stage resolution in pipelined, multistage analog-to-digital converter for video-rate applications," IEEE J. Solid-State Circuits, vol. 39, no. 8, Aug. 1992.
20. S. Bardsley, C. Dillon, R. Kummaraguntla, C. Lane, A. M. A. Ali, B. Rigsbee, and D. Combs, "A 100-dB SFDR 80-MSPS 14-bit 0.35- μm BiCMOS pipeline ADC," IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2144-2153, Sep. 2006.
21. T. N. Andersen, B. Hernes, A. Briskemyr, F. Telsto, J. Bjornsen, T. E. Bonnerud, and Ø. Moldsvor, "A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS," IEEE J. Solid-State Circuits vol. 40, no. 7, pp. 1506-1513, Jul. 2005.
22. M. Yoshioka, M. Kudo, K. Gotho, and Y.Watanabe, "A 10b 125 MS/s 40 mW pipelined ADC in 0.18 μm CMOS," in ISSCC Dig. Tech. Papers, Feb. 2005, pp. 282-283.
23. C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effect of op-amp inperfections: Autozeroing, correlated double sampling, and chopper stabilization," Proc. IEEE, vol. 84, no. 11, pp. 1584-1614, Nov. 1996.
24. D.-Y. Chang, "Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 11, pp. 2123-2132, Nov. 2004.
25. L. Sumanen, M. Waltari, and K. A. Halonen, "A 10-bit 200-MS/s CMOS parrallel pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1048-1055, Jul. 2001.
26. M. Dessouky and A. Kaiser, "Input switch configuration for rail-to-rail operation of switched opamp circuits," Electron. Lett., vol. 35, pp. 8-10, Jan. 1999.
27. H.-C. Kim, D.-K. Jeong, and W. Kim, "A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converter," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp. 795-801, Apr. 2006.
28. 2 0.13- μ CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2116-2125, Dec. 2004.