A 0.8V 10b 80MS/s 6.5mW pipelined ADC with regulated overdrive voltage blasing

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 452-454

  Yoshioka, Masato ^a   Kudo, Masahiro ^a   Mori, Toshihiko ^a   Tsukamoto, Sanroku ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS VOLTAGE; CMOS INTEGRATED CIRCUITS; LOGIC DESIGN; PIPELINE PROCESSING SYSTEMS; SOFTWARE PROTOTYPING; VOLTAGE CONTROL;

LOW-VOLTAGE DESIGN; OVERDRIVE VOLTAGE BIASING;

ANALOG TO DIGITAL CONVERSION;

EID: 34548864120     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373489     Document Type: Conference Paper

References (4)

1. K. Bult, "Analog Design in Deep Sub-Micron CMOS," Proc. ESSCIRC, pp. 128-132, Sep., 2000.
2. T. Sepke, J.K. Fiorenza, G.G. Sodini, et al., "Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies," ISSCC Dig., Tech. Papers, pp. 220-221, Feb., 2008.
3. B. Murmahn, B. Boser, "A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification," IEEE J. Solid-State Circuits, vol. 38, pp. 2040-2050, Dec. 2003.
4. R. Castello, P. R. Gray, "A High-Pertormance Micropower Switched-Capacitor Filter," IEEE J. Solid-State Circuits, vol. 20, no. 6, pp. 1122-1132, Dec, 1985.