A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 62-63

  Louwsma, Simon M ^a   Van Tuijl, Ed J M ^a   Vertregt, Maarten ^b   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

ADC; SA ADC; SAR; T H; Time interleaved

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CHANNEL CAPACITY; PIPELINES;

MULTI CHANNEL PERFORMANCE; SUCCESSIVE APPROXIMATION (SA); TIME INTERLEAVED;

CMOS INTEGRATED CIRCUITS;

EID: 39749139481     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342766     Document Type: Conference Paper

References (5)

1. K. Poultm et al., "A 20GS/s 8b ADC with a 1MB memory in 0.18μm CMOS," ISSCC Dig. Tech. Papers, pp 318-319, Feb 2003
2. S. Gupta et al., "A 1GS/s 11b Time-Interleaved ADC in 0.13 μm CMOS," ISSCC Dig. Tech. Papers, pp 264-265, Feb 2006
3. S.M. Louwsma et al. "A 1.6 GS/s.16 times interleaved track & hold with 7.6 ENOB in 0.1.2 μm CMOS," Proc. ESSCIRC. pp 343-346, Sept 2004
4. K. Nagaraj et al., "A Dual-Mode 700-Msiample/s 6-bit 200-Msampleste 7-bit A/D Converter in a 0.25 μ Digital CMOS Process." IEEE JSSC, vol. 35, pp 1760-1768, Dec 2000
5. F. Kuttner, "A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13 μm CMOS," ISSCC Dig. Tech. Papers, pp 176-177, Feb 2002