Low-temperature characterization and modeling of advanced GeOI pMOSFETs: Mobility mechanisms and origin of the parasitic conduction

Solid-State Electronics

Volumn 54, Issue 2, 2010, Pages 205-212

  Van Den Daele, W ^a,b   Augendre, E ^b   Le Royer, C ^b   Damlencourt, J F ^b   Grandchamp, B ^b   Cristoloveanu, S ^a  

^a MINATEC   (France)

^b CEA LETI   (France)

Author keywords

Ge Enrichment; GeOI; Germanium; Germanium on insulator; High metal gate; Low temperature measurements; Silicon passivation; SOI; Temperature dependent threshold voltage

Indexed keywords

GERMANIUM-ON-INSULATOR; LOW-TEMPERATURE MEASUREMENTS; METAL GATE; SOI; TEMPERATURE DEPENDENT;

GERMANIUM; LOW TEMPERATURE EFFECTS; MOSFET DEVICES; PASSIVATION; SILICON COMPOUNDS; SILICON OXIDES; SILICON WAFERS; TEMPERATURE MEASUREMENT; THRESHOLD VOLTAGE;

HOLE MOBILITY;

EID: 76349115802     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.12.020     Document Type: Article

References (24)

1. Benkart P., Kaiser A., Munding A., Bschorr M., Pfleiderer H.-J., Kohn E., et al. 3D chip stack technology using through-chip interconnects. Des Test Comput, IEEE 22 6 (2005) 512-518
2. Shang H., Frank M., Gusev E., Chu J., Bedell S., Guarini K., et al. Germanium channel MOSFETs: opportunities and challenges. IBM J Res Dev 50 4-5 (2006) 377-386
3. Yamamoto T., Yamashita Y., Harada M., Taoka N., Ikeda K., Suzuki K., et al. High performance 60 nm gate length germanium p-MOSFETs with Ni germanide metal source/drain. IEDM Tech Dig (2007) 1041-1043
4. Akatsu T., Deguet C., Sanchez L., Allibert F., Rouchon D., Signamarcheix T., et al. Germanium-on-insulator (GeOI) substrates: a novel engineered substrate for future high performance devices. Mater Sci Semicond Process 9 4-5 (2006) 444-448
5. Cristoloveanu S., and Li S. Electrical characterization of silicon-on-insulator materials and devices (1995), Springer
6. Romanjek K, Hutin L, Le Royer C, Pouydebasque A, Jaud M, Tabone C, et al. High performance 70 nm gate length germanium-on-insulator pMOSFET with high-/metal gate. In: 38th European solid-state device research conference (ESSDERC 2008), 2008. p. 75-8.
7. Dimoulas A., Tsipas P., Sotiropoulos A., and Evangelou E. Fermi-level pinning and charge neutrality level in germanium. Appl Phys Lett 89 (2006) 252110
8. Tsipas P., and Dimoulas A. Modeling of negatively charged states at the Ge surface and interfaces. Appl Phys Lett 94 (2009) 012114
9. Weber J., Janotti A., Rinke P., and Van de Walle C. Dangling-bond defects and hydrogen passivation in germanium. Appl Phys Lett 91 (2007) 142101
10. Tezuka T., Sugiyama N., Mizuno T., Suzuki M., and Takagi S. Novel fabrication technique of ultra-thin and relaxed SiGe buffer layers with high Ge fraction for sub-100 nm strained silicon-on-insulator MOSFETs. Jpn J Appl Phys, Part 1 40 4 (2001) 2866-2874
11. Vincent B., Damlencourt J., Morand Y., Pouydebasque A., Le Royer C., Clavelier L., et al. The Ge condensation technique: a solution for planar SOI/GeOI co-integration for advanced CMOS technologies?. Mater Sci Semicond Process (2008)
12. Nguyen Q., Damlencourt J., Vincent B., Clavelier L., Morand Y., Gentil P., et al. High quality germanium-on-insulator wafers with excellent hole mobility. Solid State Electron 51 9 (2007) 1172-1179
13. Damlencourt J.-F., Campidelli Y., Roure M.-C., Vincent B., Martinez E., Fillot F., et al. Epitaxial regrowth of Ge on SGOI and GeOI substrates obtained by Ge condensation. ECS Trans 6 4 (2007) 315-320
14. Eneman G, Sicart i Casain O, Simoen E, Brunco D, De Jaeger B, Satta A, et al. Analysis of junction leakage in advanced germanium P+/n junctions. In: 37th European solid state device research conference (ESSDERC 2007), 2007. p. 454-7.
15. Nsm archive website, .
16. Krishnamohan T., Krivokapic Z., Uchida K., Nishi Y., and Saraswat K. High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments. IEEE Trans Electron Dev 53 5 (2006) 990-999
17. Batail E, Monfray S, Tabone C, Kermarrec O, Damlencourt J, Gautier P, et al. Localized ultra-thin GeOI: an innovative approach to germanium channel MOSFETs on bulk Si substrates. In: IEEE international electron devices meeting (IEDM 2008), 2008. p. 1-4.
18. Ghibaudo G. New method for the extraction of MOSFET parameters. Electron Lett 24 9 (1988) 543-545
19. Le Royer C., Vincent B., Clavelier L., Damlencourt J., Tabone C., Batude P., et al. High-κ and metal-gate pMOSFETs on GeOI obtained by Ge enrichment: analysis of ON and OFF performances. IEEE Electron Dev Lett 29 6 (2008) 635-637
20. Pouydebasque A, Le Royer C, Tabone C, Romanjek K, Augendre E, Sanchez L, et al. First demonstration of deep sub-micron germanium-on-insulator pMOSFET with adapted threshold voltage. In: International symposium on VLSI technology, systems and applications (VLSI-TSA 2008), 2008. p. 16-7.
21. Martens K., Chui C., Brammertz G., De Jaeger B., Kuzum D., Meuris M., et al. On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates. IEEE Trans Electron Dev 55 2 (2008) 547
22. Groeseneken G., Colinge J., Maes H., Alderman J., Holt S., Akinwande T., et al. Temperature dependence of threshold voltage in thin-film SOI MOSFET's. IEEE Electron Dev Lett 11 8 (1990) 329-331
23. Van Den Daele W, Augendre E, Romanjek K, Le Royer C, Clavelier L, Damlencourt J-F, et al. Low-temperature measurements on germanium-on-insulator pMOSFETs: evaluation of the background doping level and modeling of the threshold voltage temperature dependency. ECS Trans Silicon-On-Insulator Technol Dev 13, in press.
24. Broqvist P., Alkauskas A., and Pasquarello A. Defect levels of dangling bonds in silicon and germanium through hybrid functionals. Phys Rev B 78 (2008) 075203