메뉴 건너뛰기




Volumn 1, Issue , 2004, Pages 533-536

Clock period minimization method of semi-synchronous circuits by delay insertion

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; LSI CIRCUITS; OPTIMIZATION; ROUTERS; SET THEORY; SYNCHRONIZATION;

EID: 13444306519     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (6)
  • 1
    • 0025464163 scopus 로고
    • Clock skew optimization
    • J.P. Fishburn. Clock skew optimization. IEEE Tranc. on Computers, 39(7):945-951, 1990.
    • (1990) IEEE Tranc. on Computers , vol.39 , Issue.7 , pp. 945-951
    • Fishburn, J.P.1
  • 2
    • 0037004749 scopus 로고    scopus 로고
    • A semi-synchronous circuit design method by clock tree modification
    • November
    • S. Ishijima, T. Utsumi, T. Oto, and A. Takahashi. A semi-synchronous circuit design method by clock tree modification. IEICE Transactions on Fundamentals, E85-A(12):2596-2602, November 2002.
    • (2002) IEICE Transactions on Fundamentals , vol.E85-A , Issue.12 , pp. 2596-2602
    • Ishijima, S.1    Utsumi, T.2    Oto, T.3    Takahashi, A.4
  • 3
    • 0036999287 scopus 로고    scopus 로고
    • A clustering based fast clock schedule algorithm for light clock-trees
    • November
    • M. Saitoh, M. Azuma, and A. Takahashi. A clustering based fast clock schedule algorithm for light clock-trees. IEICE Transactions on Fundamentals, E85-A(12):2756-2763, November 2002.
    • (2002) IEICE Transactions on Fundamentals , vol.E85-A , Issue.12 , pp. 2756-2763
    • Saitoh, M.1    Azuma, M.2    Takahashi, A.3
  • 4
    • 0030651638 scopus 로고    scopus 로고
    • Performance and reliability driven clock scheduling of sequential logic circuits
    • A. Takahashi and Y. Kajitani. Performance and reliability driven clock scheduling of sequential logic circuits. In ASP-DAC'97, pages 37-43, 1997.
    • (1997) ASP-DAC'97 , pp. 37-43
    • Takahashi, A.1    Kajitani, Y.2
  • 5
    • 13444253290 scopus 로고    scopus 로고
    • A circuit optimization method by the register path modification in consideration of the range of feasible clock timing
    • In Japanese
    • T. Yasui, K. Kurokawa, M. Toyonaga, and A. Takahashi. A circuit optimization method by the register path modification in consideration of the range of feasible clock timing. In DA Symposium 2002, pages 259-264, 2002. In Japanese.
    • (2002) DA Symposium 2002 , pp. 259-264
    • Yasui, T.1    Kurokawa, K.2    Toyonaga, M.3    Takahashi, A.4
  • 6
    • 13444260318 scopus 로고    scopus 로고
    • Clock period minimization of semi-synchronous circuits by gate-level delay insertion
    • November
    • T. Yoda and A. Takahashi. Clock period minimization of semi-synchronous circuits by gate-level delay insertion. IEICE Transactions on Fundamentals, E82-A(11):2383-2389, November 1999.
    • (1999) IEICE Transactions on Fundamentals , vol.E82-A , Issue.11 , pp. 2383-2389
    • Yoda, T.1    Takahashi, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.