Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 521-528

  Xue, Jiying ^a   Ye, Zuochang ^a   Deng, Yangdong ^a   Wang, Hongrui ^a   Yang, Liu ^a   Yu, Zhiping ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC NETWORK ANALYSIS; MOSFET DEVICES; STRESS ANALYSIS; THRESHOLD VOLTAGE; TIMING CIRCUITS;

CIRCUIT BEHAVIORS; CIRCUIT PERFORMANCE; LAYOUT DEPENDENCES; LAYOUT DEPENDENTS; NON-UNIFORM DISTRIBUTION; OPTIMIZATION STRATEGY; PROCESS INFORMATION; SHALLOW TRENCH ISOLATION;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 76349091335     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1687399.1687497     Document Type: Conference Paper

References (25)

1. N. Stutzke, B. J. Cheek and S. Kumar, "Effects of circuit-level stress on inverter performance and MOSFET characteristics," In Proc. Integrated Reliability Workshop Final Report, pp.71-79, 2003.
2. M. Miyamoto, H. Ohta, Y. Kumagai, et al., "Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics," IEEE Trans. Electron Device. Vol.51, No.3, 2004.
3. V. Moroz et al., "The Impact of Layout on Stress-Enhanced Transistor Performance," in Proc. SISPAD, pp. 143-146, 2005.
4. Y. Luo and D. K. Nayak, "Enhancement of CMOS Performance by Process-Induced Stress," IEEE Trans. Semiconductor Manufacturing, Vol. 18, No. 1,2005.
5. P. B. Y. Tan, "Analysis of Deep Submicron CMOS Transistor Vtlin and Idsat versus Channel Width," In Proc. APMC, pp.1450-1452, 2006.
6. R. A. Bianchi, G. Bouche, O. Roux-dit-Buisson, "Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance," In Proc. IEDM, pp. 117-120, 2002.
7. K. Su, Y. Sheu, C. Lin, et. al., "A Scaleable Model for STI Mechanical Stress Effect on Layout Dependence of MOS Electrical Characteristics," In Proc. CICC, pp. 245-248, 2003.
8. P. B. Y. Tan, "Compact Modeling of Mechanical STI y-Stress Effect," In Proc. ICSICT, pp.1450-1452, 2006.
9. A. B. Kahng, et. al., "Exploiting STI Stress for Performance," In Proc. ICCAD, pp.83-90, 2007.
10. A. B. Kahng, et. al., "Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion," IEEE Trans. CAD, Vol.27, No.7, 2008,.
11. P. B. Y. Tan, et. al., "Layout Dependence Effect on High Speed CMOS Transistor Leakage Current," In Proc. APACE, 2005.
12. V. Joshi, et. al., "Leakage Power Reduction Using Stress-Enhanced Layouts," In Proc. DAC, pp.71-79, 2008.
13. R. O. Topaloglu, "Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization," In Proc. CICC, pp.619-622, 2007.
14. A. T. Tilke, C. Stapelmann and M. Eller, "Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance," IEEE Trans. Semiconductor Manufacturing, Vol. 20, No. 2, May. 2007.
15. J. J. Wortman and R. A. Evans, "Young's Modulus, Shear Modulus, Poisson's Ratio in Silicon and Germanium," Journal of Applied Physics, Vol. 36, pp. 153-156, 1965.
16. H. A. Rueda, "Modeling of mechanical stress in silicon isolation technology and its influence on device characteristics," Ph.D. dissertation, Univ.Florida, 1999.
17. H. Tsuno, K. Anzai, M. Matsumura, et. al. "Advanced Analysis and Modeling of MOSFET Characteristic Fluctuation Caused by Layout Variation," In Proc. VISL , pp.204-205, 2007.
18. Liu Yang, Xiaojian Li, Lilin Tian, and Zhiping Yu,, "Simulation of layout-dependent STI stress and its impact on circuit performance," to be presented In Proc. SISPAD, Sept. 2009.
19. I. Goroff and L. Kleinman, "Deformation Potentials in Silicon. III. Effects of a General Strain on Conduction and Valence Levels," Physical Review, Vol. 132, pp. 1080-1084, 1963.
20. J. C. Hensel and G. Feher, "Cyclotron Resonance Experiments in Uniaxially Stressed Silicon: Valence Band Inverse Mass Parameters and Deformation Potentials," Physical Review, vol. 129, pp. 1041-1062, 1963.
21. S. Dhar, H. Kosina and V. Palankovski, et. al. "Electron Mobility Model for Strained-Si Devices," IEEE Trans. Electron Device. Vol.52, No.4, 2005.
22. V. Chan, K. Rim, M. Ieong, et al. "Strain for CMOS performance improvement," In Proc. CICC, pp.667-674,. 2005.
23. S. Mukhopadhyay, S. Member and A. Raychowdhury, et al. "Accurate Estimation of Total Leakage in Nanometer- Scale Bulk CMOS Circuits Based on Device Geometry and Doping Profile," IEEE Trans. CAD, Vol. 24, No.3 2005.
24. T. Li and Z. Yu. "Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and modeling," In Proc. DAC, pp. 594-599, 2008.
25. From private communication, 2009.