-
1
-
-
51549090072
-
High performance cmosfet technology for 45nm generation and scalability of stress-induced mobility enhancement technique
-
A. Oishi and O. Fujii. High performance cmosfet technology for 45nm generation and scalability of stress-induced mobility enhancement technique. In Proc. IEDM, pages 194-197, 2005.
-
(2005)
Proc. IEDM
, pp. 194-197
-
-
Oishi, A.1
Fujii, O.2
-
2
-
-
15244338765
-
Accurate estimation of total leakage in nanometer-scale bulk cmos circuits based on device geometry and doping profile
-
March
-
S. Mukhopadhyay, S. Member, A. Raychowdhury, and K. Roy. Accurate estimation of total leakage in nanometer-scale bulk cmos circuits based on device geometry and doping profile. IEEE Trans. CAD, 24(3):363-381, March 2005.
-
(2005)
IEEE Trans. CAD
, vol.24
, Issue.3
, pp. 363-381
-
-
Mukhopadhyay, S.1
Member, S.2
Raychowdhury, A.3
Roy, K.4
-
3
-
-
51549100905
-
-
Semiconductor industry association, available at
-
Semiconductor industry association, "international technology roadmap for semiconductors," 2006. available at: http://public.itrs.net.
-
(2006)
-
-
-
4
-
-
51549118560
-
-
The high-k solution. In IEEE SPECTRUM, Oct. 2007.
-
The high-k solution. In IEEE SPECTRUM, Oct. 2007.
-
-
-
-
5
-
-
34547294294
-
Characterizing process variation in nanometer cmos
-
K. Agarwal and S. Nassif. Characterizing process variation in nanometer cmos. In Proc. DAC, pages 396-339, 2007.
-
(2007)
Proc. DAC
, pp. 396-339
-
-
Agarwal, K.1
Nassif, S.2
-
6
-
-
34547287531
-
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
-
R. Singhal, A. Balijepalli, A. Subramaniam, F. Liu, S. Nassif, and Y. Cao. Modeling and analysis of non-rectangular gate for post-lithography circuit simulation. In Proc. DAC, pages 823-828, 2007.
-
(2007)
Proc. DAC
, pp. 823-828
-
-
Singhal, R.1
Balijepalli, A.2
Subramaniam, A.3
Liu, F.4
Nassif, S.5
Cao, Y.6
-
7
-
-
27944470947
-
Full-chip analysis of leakage power under process variations, including spatial correlations
-
H. Chang and S. Sapatnekar. Full-chip analysis of leakage power under process variations, including spatial correlations. In Proc. DAC, pages 523-530, 2005.
-
(2005)
Proc. DAC
, pp. 523-530
-
-
Chang, H.1
Sapatnekar, S.2
-
8
-
-
27944464454
-
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance
-
A. Srivastava, S. Shah, K. Agarwal, D. Sylvester, D. Blaauw, and S. Director. Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. In Proc. DAC, 2005.
-
(2005)
Proc. DAC
-
-
Srivastava, A.1
Shah, S.2
Agarwal, K.3
Sylvester, D.4
Blaauw, D.5
Director, S.6
-
9
-
-
34547156269
-
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions
-
X. Li, J. Le, and L. T. Pleggi. Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. In Proc. DAC, pages 103-110, 2006.
-
(2006)
Proc. DAC
, pp. 103-110
-
-
Li, X.1
Le, J.2
Pleggi, L.T.3
-
10
-
-
34547328040
-
Width-dependent statistical leakage modeling for random dopant induced threshold voltage shift
-
J. Gu, S. S Sapatnekar, and C. Kim. Width-dependent statistical leakage modeling for random dopant induced threshold voltage shift. In Proc. DAC, pages 87-92, 2007.
-
(2007)
Proc. DAC
, pp. 87-92
-
-
Gu, J.1
Sapatnekar, S.S.2
Kim, C.3
-
11
-
-
34547369754
-
Modeling and estimation of full-chip leakage current considering within-die correlation
-
K. R. Heloue, N. Azizi, and F. N Najm. Modeling and estimation of full-chip leakage current considering within-die correlation. In Proc. DAC, pages 93-98, 2007.
-
(2007)
Proc. DAC
, pp. 93-98
-
-
Heloue, K.R.1
Azizi, N.2
Najm, F.N.3
-
12
-
-
34547319657
-
Statistical analysis of full-chip leakage power considering junction tunneling leakage
-
Y. Wang, G. Chen, and T. Li. Statistical analysis of full-chip leakage power considering junction tunneling leakage. In Proc. DAC, pages 99-102, 2007.
-
(2007)
Proc. DAC
, pp. 99-102
-
-
Wang, Y.1
Chen, G.2
Li, T.3
-
14
-
-
34547223772
-
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis
-
J. Singh and S. Sapatnekar. Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. In Proc. DAC, pages 155-162, 2006.
-
(2006)
Proc. DAC
, pp. 155-162
-
-
Singh, J.1
Sapatnekar, S.2
-
15
-
-
16244393708
-
Asymptotic probability extraction for non-normal distributions of circuit performance
-
X. Li, J. Le, P. Gopalakrishnan, and L. T. Pleggi. Asymptotic probability extraction for non-normal distributions of circuit performance. In Proc. ICCAD, pages 2-9, 2004.
-
(2004)
Proc. ICCAD
, pp. 2-9
-
-
Li, X.1
Le, J.2
Gopalakrishnan, P.3
Pleggi, L.T.4
-
16
-
-
33751436870
-
Projection-based performance modeling for inter/intra-die variations
-
X. Li, J. Le, L. Pileggi, and A. Strojwas. Projection-based performance modeling for inter/intra-die variations. In Proc. ICCAD, pages 721-727, 2005.
-
(2005)
Proc. ICCAD
, pp. 721-727
-
-
Li, X.1
Le, J.2
Pileggi, L.3
Strojwas, A.4
-
17
-
-
33746369469
-
Static noise margin variation for sub-threshold sram in 65-nm cmos
-
Jul
-
B. H. Calhoun and A. P. Chandrakasan. Static noise margin variation for sub-threshold sram in 65-nm cmos. IEEE JSSC, 41(7):1673-1679, Jul. 2006.
-
(2006)
IEEE JSSC
, vol.41
, Issue.7
, pp. 1673-1679
-
-
Calhoun, B.H.1
Chandrakasan, A.P.2
|