Compact modeling of mechanical STI y-stress effect

ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Volumn , Issue , 2006, Pages 1450-1452

  Tan, Philip Beow Yew ^a,b   Kordesch, Albert Victor ^a   Sidek, Othman ^b  

^a SILTERRA MALAYSIA SDN BHD   (Malaysia)

^b SCHOOL OF CHEMICAL ENGINEERING   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; INTEGRATED CIRCUIT LAYOUT; PARAMETER EXTRACTION; SEMICONDUCTOR DEVICE MODELS;

MOBILITY PARAMETERS; SHALLOW TRENCH ISOLATION (STI) Y-STRESS;

MOS DEVICES;

EID: 34547248680     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2006.306233     Document Type: Conference Paper

References (7)

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2. C. H. Ge et. al, "Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering," International Electron Device Meeting, pp.73 (2003).
3. M. Miyamoto et al., "Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics," IEEE Transactions on Electron Devices, vol.51, no.3 (2004).
4. X. Xi et al., "BSIM4.3.0 MOSFET Model User's Manual," University of California, Berkeley, pp. 13.1-13.7(2003).
5. P. B. Y. Tan et. al., "Hook Shaped Drain Current vs Width Curve of 130nm CMOS Technology," National Symposium of Microelectronic (NSM), (2005).
6. P. B. Y. Tan et. al., "Analysis of Deep Submicron CMOS Transistor Vtlin and Idsat versus Channel Width," Asia-Pacific Microwave Conference (APMC), (2005).
7. C. Pacha et al., "Impact of STI-Induced Stress, Inverse Narrow Width Effect, and Statistical Vth Variations on Leakage Currents in 120nm CMOS," Solid-State Device Research Conference (ESSDERC), pp. 397-400 (2004).