Settling time optimization for three-stage CMOS amplifier topologies

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 12, 2009, Pages 2569-2582

  Pugliese, Andrea ^a   Amoroso, Francesco Antonio ^a   Cappuccino, Gregorio ^a   Cocorullo, Giuseppe ^a  

^a UNIVERSITY OF CALABRIA   (Italy)

Author keywords

Analog design; Frequency compensation; Operational amplifiers; Transient response

Indexed keywords

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT DESIGN; TOPOLOGY; TRANSIENT ANALYSIS;

ANALOG DESIGN; COMPENSATION NETWORK; DESIGN APPROACHES; DESIGN METHODOLOGY; FREQUENCY COMPENSATION; LOAD CAPACITANCE; SETTLING BEHAVIOR; THREE STAGE OPERATIONAL AMPLIFIER;

OPERATIONAL AMPLIFIERS;

EID: 75749129882     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2017133     Document Type: Article

References (29)

1. 2 90-nm CMOS pipeline ADC for flat panel display applications," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2688-2695, Dec. 2007.
2. H. L. Lee and P. K. T. Mok, "An SC voltage doubler with pseudo- continuous output regulation using a three-stage switchable opamp," IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1216-1229, Jun. 2007.
3. H.-C. Lin, H.-H. Wu, and T.-Y. Chang, "An active-frequency compensation scheme for CMOS low-dropout regulators with transient-response improvement," IEEE Trans. On Circ. And Syst. II: Expr. Briefs, vol. 55, no. 9, pp. 853-857, Sep. 2008.
4. W.-J. Huang and S.-I. Liu, "Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array," IET Circuits, Devices Syst., vol. 2, no. 3, pp. 306-316, Mar. 2007.
5. A. D. Grasso, G. Palumbo, and S. Pennisi, "Analytical comparison of frequency compensation techniques in three-stage amplifiers," Int. J. Circ. Theory Applicat., vol. 36, no. 1, pp. 53-80, Jan. 2008.
6. S. O. Cannizzaro, A. D. Grasso, R. Mita, G. Palumbo, and S. Pennisi, "Design procedures for three-stage CMOS OTAs with nested-Miller compensation," IEEE Trans. Circuits Syst. I, Regul. Papers, vol. 54, no. 5, pp. 933-940, May 2007.
7. K. N. Leung and P. K. T. Mok, "Analysis of multistage amplifier-frequency compensation," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 9, pp. 1041-1056, Sep. 2001.
8. G. Palumbo and S. Pennisi, Feedback Amplifiers Theory and Design. Boston, MA: Kluwer, 2002.
9. K. N. Leung and P. K. T. Mok, "Right-half plane zero removal technique for low-voltage low-power nested Miller compensation," Proc. IEEE Electron., Circuits, Syst., vol. 2, pp. 599-602, Sep. 1999, 1999.
10. G. Palumbo and S. Pennisi, "Design methodology and advances in nested-Miller compensation," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 7, pp. 893-903, Jul. 2002.
11. A. D. Grasso, G. Palumbo, and S. Pennisi, "Three-stage CMOS OTA for large capacitive loads with efficient frequency compensation scheme," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 10, pp. 1044-1048, Oct. 2006.
12. R. G. H. Eschauzier and J. H. Huiising, Frequency Compensation Techniques for Low-Power Operational Amplifier. Boston, MA: Kluwer, 1995.
13. R. G. H. Eschauzier and J. H. Huiising, "A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1709-1716, Dec. 1992.
14. F. You, S. Embabi, and E. Sanchez-Sinencio, "Multistage amplifier topologies with nested Gm-C compensation," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2000-2011, Dec. 1997.
15. K. N. Leung and P. K. T. Mok, "Nested Miller compensation in low-power CMOS design," IEEE Trans. Circuits Syst. II, vol. 48, pp. 388-394, Apr. 2001.
16. K. N. Leung, P. K. T. Mok, and W. H. Ki, "Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design," Proc. IEEE Circuits Syst. Int. Symp., vol. 2, pp. 616-619, Jul. 1999.
17. K. N. Leung, P. K. T. Mok, W. H. Ki, and J. K. O. Sin, "Three-stage large capacitive load amplifier with damping-factor-control frequency compensation," IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 221-230, Feb. 2000.
18. H. Lee and P. K. T. Mok, "Active-feedback frequency-compensation technique for low-power multistage amplifiers," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 511-520, Mar. 2003.
19. H. Lee and P. K. T. Mok, "Advances in active-feedback frequency compensation with power optimization and transient improvement," IEEE Trans. Circuits Syst. I, Reg. Paper, vol. 51, no. 9, pp. 1690-1696, Sep. 2004.
20. X. Peng and W. Sansen, "Transconductance with capacitances feedback compensation for multistage amplifiers," IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1514-1520, Jul. 2005.
21. H. Lee, K. N. Leung, and P. K. T. Mok, "A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation," IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1739-1744, Oct. 2003.
22. X. Peng and W. Sansen, "AC boosting compensation scheme for low- power multistage amplifiers," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2074-2077, Nov. 2004.
23. H. C. Yang and D. J. Allstot, "Considerations for fast settling operational amplifiers," IEEE Trans. Circuits Syst., vol. 37, no. 3, pp. 326-334, Mar. 1990.
24. A. Pugliese, G. Cappuccino, and G. Cocorullo, "Nested Miller compensation capacitor sizing rules for fast-settling amplifier design," IEE Electron. Lett., vol. 41, no. 10, pp. 573-575, May 2005.
25. A. Pugliese, G. Cappuccino, and G. Cocorullo, "Design procedure for settling time minimization in three-stage nested-Miller amplifiers," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 1, pp. 1-5, Jan. 2008.
26. A. Pugliese, G. Cappuccino, and G. Cocorullo, "Settling time minimization of operational amplifiers," in Lecture Notes in Computer Science. Berlin, Germany: Springer-Verlag, 2007, vol. 4644, pp. 107-116.
27. A. Marques, Y. Geerts, M. Steyaert, and W. Sansen, "Settling time analysis of third order systems," in Proc. IEEE Int. Conf. Electron., Circuits, Syst., Sep. 1998, vol. 2, pp. 505-508.
28. M. E. Schlarmann and R. L. Geiger, "Relationship between amplifier settling time and pole-zero placements for second-order systems," in Proc. Symp. Circuits Syst., Aug. 2000, vol. 1, pp. 54-59.
29. R. J. Baker, CMOS Mixed-Signal Circuit Design. Piscataway, NJ: Wiley, 2002.