Nested Miller compensation capacitor sizing rules for fast-settling amplifier design

Electronics Letters

Volumn 41, Issue 10, 2005, Pages 573-575

  Pugliese, A ^a   Cappuccino, G ^a   Cocorullo, G ^a  

^a UNIVERSITY OF CALABRIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITANCE; CAPACITORS; CLOSED LOOP CONTROL SYSTEMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DAMPING; ELECTRIC NETWORK TOPOLOGY; SIGNAL PROCESSING; SYSTEM STABILITY; TRANSFER FUNCTIONS;

CLOSED-LOOP RESPONSE STABILITY; MILLER FREQUENCY COMPENSATION (MFC); OPEN-LOOP TRANSFER FUNCTIONS; PHASE MARGIN;

AMPLIFIERS (ELECTRONIC);

EID: 19944373756     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20050398     Document Type: Article

References (4)

1. Eschauzier, R.G.H., and Huijsing, J.H.: 'Frequency compensation techniques for low-power operational amplifiers' (Kluwer, Boston, MA, 1995)
2. Palumbo, G., and Pennisi, S.: 'Design methodology and advances in nested-Miller compensation', IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 2002, 49, (7)
3. Yang, H.C., and Allstot, D.J.: 'Considerations for fast settling operational amplifiers', IEEE Trans. Circuits Syst., 1990, 37, (3)
4. Marques, A., et al.: 'Settling time analysis of third order systems'. Proc. IEEE Int. Conf. on Electronics, Circuits and Systems, 1998, Vol. 2, pp. 505-508