Right-half-plane zero removal technique for low-voltage low-power nested Miller compensation CMOS amplifier

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 1999, Pages 599-602

  Leung, Ka Nang ^a   Mok, Philip K T ^a   Ki, Wing Hung ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

POWER SUPPLY CIRCUITS;

CMOS AMPLIFIERS; LOW POWER CMOS; LOW VOLTAGES; NEGATIVE POWER SUPPLY; NESTED MILLER COMPENSATION; PHASE MARGINS; RIGHT HALF PLANE ZERO; SETTLING TIME;

AMPLIFIERS (ELECTRONIC);

EID: 0003051341     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1999.813179     Document Type: Conference Paper

References (6)

1. R.G.H. Eschauzier, L.P.T. Kerklaan and J.H. Huijsing, "A 100-MHz 100-dB Operational Amplifier with Multipart! Nested Miller Compensation Structure", IEEE Journal of Solid-State Circuits, vol. 27, pp.1709-1717, 1992.
2. S. Pernici, G. Nicollini and R. Castello, "A CMOS Low-Distortion Fully Differential Power Amplifier with Double Nested Miller Compensation", IEEE Journal Solid-State Circuits, vol. 28, pp.758-763, 1993.
3. P.R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuit, 2nd edition. New York: Wiley, 1984.
4. R. Gregorian and G.C. Ternes, Analog MOS Integrated Circuits for Signal Processing, 1st edition. New York: Wiley, 1986.
5. G.C. Temes and J.W. LaPatra, Introduction to Circuit Synthesis and Design, 1st edition. USA:McGraw-Hill, 1977.
6. B.Y Kamath, R.G. Meyer and P.R. Gray, "Relationship between Frequency Response and Settling Time of Operational Amplifier", IEEE Journal of Solid-State Circuits, vol. 9, pp.347-352, 1974.