Design methodology and advances in nested-Miller compensation

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 49, Issue 7, 2002, Pages 893-903

  Palumbo, Gaetano ^a,b   Pennisi, Salvatore ^a,b  

^a IEEE   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

Amplifiers; Analog integrated circuits; Circuit stability; CMOS analog integrated circuits; CMOSFET power amplifiers; Compensation; Feedback amplifiers; Feedback circuits; Frequency compensation; Multistage amplifier; Zero compensation

Indexed keywords

ANALOG INTEGRATED CIRCUITS; CIRCUIT STABILITY; FEEDBACK CIRCUITS; FREQUENCY COMPENSATION; MULTISTAGE AMPLIFIER; NESTED MILLER COMPENSATION; NULLING RESISTOR; PHASE MARGIN; RIGHT HALF PLANE ZERO; ZERO COMPENSATION;

CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FEEDBACK AMPLIFIERS; FREQUENCIES; INTEGRATED CIRCUIT LAYOUT; OPERATIONAL AMPLIFIERS; OPTIMIZATION; POLES AND ZEROS; RESISTORS; TRANSCONDUCTANCE;

POWER AMPLIFIERS;

EID: 0036647564     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2002.800463     Document Type: Article

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