Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1999, Pages

  Leung, Ka Nang ^a   Mok, Philip K T ^a   Ki, Wing Hung ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; GAIN CONTROL; INTEGRATED CIRCUIT LAYOUT; RESISTORS; TRANSCONDUCTANCE; TRANSFER FUNCTIONS; TRANSIENTS;

FEEDFORWARD TRANSCONDUCTANCE; NESTED MILLER COMPENSATION; NULL RESISTOR; PHASE MARGIN; POWER SUPPLY REJECTION RATIO;

OPERATIONAL AMPLIFIERS;

EID: 0004433738     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (8)