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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 4, 2001, Pages 388-394

Nested Miller compensation in low-power CMOS design

(2) Leung, K N a Mok, P K T a

a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY (Hong Kong)

Author keywords

Feedforward transconductance stage; Nested Miller compensation; Nulling resistor

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC RESISTANCE; FREQUENCY RESPONSE; RESISTORS; STABILITY; TRANSCONDUCTANCE;

FEEDFORWARD TRANSCONDUCTANCE STAGE; NESTED MILLER COMPENSATION AMPLIFIER; NULLING RESISTOR; TRANSIENT RESPONSE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035300253 PISSN: 10577130 EISSN: None Source Type: Journal
DOI: 10.1109/82.933799 Document Type: Article

Times cited : (105)

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