Comprehensive analysis of random telegraph noise instability and its scaling in deca-nanometer flash memories

IEEE Transactions on Electron Devices

Volumn 56, Issue 8, 2009, Pages 1746-1752

  Ghetti, Andrea ^a   Monzio Compagnoni, Christian ^b,c   Spinelli, Alessandro S ^b,c,d   Visconti, Angelo ^a  

^a Numonyx   (Italy)

^b POLITECNICO DI MILANO   (Italy)

^c Italian University Nano Electronics Team IUNET   (Italy)

^d IFN CNR   (Italy)

Author keywords

Flash memories; Random telegraph noise (RTN); Semiconductor device modeling; Threshold voltage instability

Indexed keywords

ACTIVE AREA; BIAS CONDITIONS; CELL GEOMETRIES; COMPREHENSIVE ANALYSIS; CRITICAL PARAMETER; DECA-NANOMETER; EXPONENTIAL TAIL; OXIDE THICKNESS; RANDOM PLACEMENT; RANDOM TELEGRAPH NOISE; RANDOM TELEGRAPH NOISE (RTN); SCALING TRENDS; SEMICONDUCTOR DEVICE MODELING; STATISTICAL DISTRIBUTION; SUBSTRATE DOPING; TCAD SIMULATION;

CELL MEMBRANES; PARAMETER ESTIMATION; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR SWITCHES; STABILITY; TELEGRAPH; THREE DIMENSIONAL; THRESHOLD VOLTAGE;

FLASH MEMORY;

EID: 68349125520     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2024031     Document Type: Article

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