The Bulk Multicore architecture for improved programmability

Communications of the ACM

Volumn 52, Issue 12, 2009, Pages 58-65

  Torrellas, Josep ^a   Ceze, Luis ^b   Tuck, James ^c   Cascaval, Calin ^d   Montesinos, Pablo ^e   Ahn, Wonsun ^a   Prvulovic, Milos ^f  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF WASHINGTON   (United States)

^c NORTH CAROLINA STATE UNIVERSITY   (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

^e SAMSUNG INFORMATION SYSTEMS AMERICA   (United States)

^f GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC BLOCKS; CACHE COHERENCE; DYNAMIC INSTRUCTIONS; HIGH-SPEED; MEMORY CONSISTENCY; MULTI CORE; MULTICORE ARCHITECTURES; NOVEL HARDWARE; PARALLEL PROGRAM; PROGRAMMABILITY; RUNTIME SYSTEMS; SCALABLE HARDWARE;

COMPUTER SOFTWARE; PARALLEL ARCHITECTURES; PARALLEL PROGRAMMING; SOFTWARE ARCHITECTURE;

PROGRAM DEBUGGING;

EID: 71149094440     PISSN: 00010782     EISSN: 15577317     Source Type: Journal    
DOI: 10.1145/1610252.1610271     Document Type: Article

References (21)

1. Ahn, W., Qi, S., Lee, J.W., Nicolaides, M., Fang, x., Torrellas, J., Wong, D., and Midkiff, S. BulkCompiler: High-performance sequential consistency through cooperative compiler and hardware support. in Proceedings of the International Symposium on Microarchitecture (New York City, Dec. 12-16). IEEE Press, 2009.
2. Ceze, L., Tuck, J., Montesinos, P., and Torrellas, J. BulkSC: Bulk enforcement of sequential consistency. in Proceedings of the International Symposium on Computer Architecture (San Diego, CA, June 9-13). ACM Press, New York, 2007, 278-289.
3. Ceze, L., Tuck, J., Cascaval, C., and Torrellas, J. Bulk disambiguation of speculative threads in multiprocessors. in Proceedings of the International Symposium on Computer Architecture (Boston, MA, June 17-21). IEEE Press, 2006, 227-238.
4. Choi, J., Lee, K., Loginov, A., O'Callahan, R., Sarkar, V., and Sridharan, M. effcient and precise data-race detection for multithreaded object-oriented programs. in Proceedings of the Conference on Programming Language Design and Implementation (Berlin, Germany, June 17-19). ACM Press, New York, 2002, 258-269.
5. Hammond, L., Wong, V., Chen, M., Carlstrom, B.D., Davis, J.D., Hertzberg, B., Prabhu, M.K., Wijaya, H., Kozyrakis, C., and Olukotun, K. Transactional memory coherence and consistency. in Proceedings of the International Symposium on Computer Architecture (München, Germany, June 19-23). IEEE Press, 2004, 102-113.
6. Herlihy M. and Moss, J.e.B. Transactional memory: Architectural support for lock-free data structures. in Proceedings of the International Symposium on Computer Architecture (San Diego, CA, May 16-19). IEEE Press, 1993, 289-300.
7. Isard, M. and Birrell, A. Automatic mutual exclusion. in Proceedings of the Workshop on Hot Topics in Operating Systems (San Diego, CA, May 7-9). USeNix, 2007.
8. Kuck, D. Facing up to software's greatest challenge: Practical parallel processing. Computers in Physics 11, 3 (1997).
9. Lamport, L. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers C-28, 9 (Sept. 1979), 690-691.
10. Lamport, L. Time, clocks, and the ordering of events in a distributed system. Commun. ACM 21, 7 (July 1978), 558-565.
11. Lu, S., Tucek, J., Qin, F., and Zhou, Y. AViO: Detecting atomicity violations via access interleaving invariants. in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (San Jose, CA, Oct. 21-25). ACM Press, New York, 2006, 37-48.
12. Minh, C., Trautmann, M., Chung, J., McDonald, A., Bronson, N., Casper, J., Kozyrakis, C., and Olukotun, K. An effective hybrid transactional memory with strong isolation guarantees. in Proceedings of the International Symposium on Computer Architecture (San Diego, CA, June 9-13). ACM Press, New York, 2007, 69-80.
13. Montesinos, P., Ceze, L., and Torrellas, J. DeLorean: Recording and deterministically replaying shared-memory multiprocessor execution effciently. In Proceedings of the International Symposium on Computer Architecture (Beijing, June 21-25). IIII Press, 2008, 289-300.
14. Musuvathi, M. and Qadeer, S. iterative context bounding for systematic testing of multithreaded programs. in Proceedings of the Conference on Programming Language Design and Implementation (San Diego, CA, June 10-13). ACM Press, New York, 2007, 446-455.
15. Narayanasamy, S., Pereira, C., and Calder, B. Recording shared memory dependencies using strata. in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (San Jose, CA, Oct. 21-25). ACM Press, New York, 2006, 229-240.
16. Prvulovic, M. and Torrellas, J. Reenact: Using thread-level speculation mechanisms to debug data races in multithreaded codes. in Proceedings of the International Symposium on Computer Architecture (San Diego, CA, June 9-11). IEEE Press, 2003, 110-121.
17. Sohi, G., Breach, S., and Vijayakumar, T. Multiscalar processors. in Proceedings of the International Symposium on Computer Architecture (Santa Margherita Ligure, italy, June 22-24). ACM Press, New York, 1995, 414-425.
18. Tuck, J., Ahn, W., Ceze, L., and Torrellas, J. SoftSig: Software-exposed hardware signatures for code analysis and optimization. in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (Seattle, WA, Mar. 1-5). ACM Press, New York, 2008, 145-156.
19. Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenstrom, P., Smith, J.E., and Valero, M. implementing kilo-instruction multiprocessors. in Proceedings of the International Conference on Pervasive Services (Santorini, Greece, July 11-14). IEEE Press, 2005, 325-336.
20. Xu, M., Bodik, R., and Hill, M.D. A 'fight data recorder' for enabling full-system multiprocessor deterministic replay. in Proceedings of the International Symposium on Computer Architecture (San Diego, CA, June 9-11). IEEE Press, 2003, 122-133.
21. Yen, L., Bobba, J., Marty, M., Moore, K., Volos, H., Hill, M., Swift, M., and Wood, D. LogTM-Se: Decoupling hardware transactional memory from caches. in Proceedings of the International Symposium on High Performance Computer Architecture (Phoenix, AZ, Feb. 10-14). IEEE Press, 2007, 261-272. (Pubitemid 47208171)