SoftSig: Software-exposed hardware signatures for code analysis and optimization

Operating Systems Review (ACM)

Volumn 42, Issue 2, 2008, Pages 145-156

  Tuck, James ^a   Ahn, Wonsun ^b   Ceze, Luis ^c   Torrellas, Josep ^b  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c UNIVERSITY OF WASHINGTON   (United States)

Author keywords

Memory disambiguation; Multi core architectures; Runtime optimization

Indexed keywords

CODE ANALYSIS; MEMORY DISAMBIGUATION; MULTI-CORE ARCHITECTURES; RUNTIME OPTIMIZATION;

CODES (SYMBOLS); COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER SOFTWARE; OPTIMIZATION;

ELECTRONIC DOCUMENT IDENTIFICATION SYSTEMS;

EID: 77957809930     PISSN: 01635980     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1346281.1346300     Document Type: Conference Paper

References (31)

1. D. Bernstein, D. Cohen, and D. E. Maydan, "Dynamic Memory Disambiguation, for Array References," in International Symposium on Microarchitecture, November 1994.
2. B. Bloom, "Space/Time Trade-Offs in Hash Coding with Allowable Errors," Communications of the ACM, vol. 11, July 1970.
3. L. Ceze, J. Tuck, C. Cascaval, and J. Torrellas, "Bulk Disambiguation of Speculative Threads in Multiprocessors," in International Symposium on Computer Architecture, June 2006.
4. L. Ceze, J. Tuck, P. Montesinos, and J. Torrellas, "BulkSC: Bulk Enforcement of Sequential Consistency," in International Symposium on Computer Architecture, June 2007.
5. D. A. Connors, H. C. Hunter, B.-C. Cheng, and W.-M. W. Hwu, "Hardware Support for Dynamic Activation of Compiler-Directed Computation Reuse," in International Conference on Architectural Support for Programming Languages and Operating Systems, November 2000.
6. D. A. Connors and W.-M. W. Hwu, "Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results," in International Symposium on Microarchitecture, November 1999.
7. T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms. MIT Press, Cambridge, MA, 2001.
8. Y. Ding and Z. Li, "A Compiler Scheme for Reusing Intermediate Computation Results," in International Symposium on Code Generation and Optimization, March 2004.
9. D. M. Gallagher, W. Y. Chen, S. A. Mahlke, J. C. Gyllenhaal, and W.-M. W. Hwu, "Dynamic Memory Disambiguation Using the Memory Conflict Buffer," in International Conference on Architectural Support for Programming Languages and Operating Systems, October 1994.
10. J. Huang and D. Lilja, "Exploiting Basic Block Value Locality with Block Reuse," in International Symposium on High Performance Computer Architecture, January 1999.
11. Intel Corporation, Intel 64 and IA-32 Architectures Software Developer's Manual. Volume 3B: System Programming Guide, Part II, November 2007.
12. V. Krishnan and J. Torrellas, "A Chip-Multiprocessor Architecture with Speculative Multithreading," IEEE Trans. on Computers, September 1999.
13. J. Lin, T. Chen, W.-C. Hsu, and P.-C. Yew, "Speculative Register Promotion Using Advanced Load Address Table (ALAT)," in International Symposium on Code Generation and Optimization, March 2003.
14. M. Lipasti, C. Wilkerson, and J. Shen, "Value Locality and Load Value Prediction," in International Conference on Architectural Support for Programming Languages and Operating Systems, October 1996.
15. M. H. Lipasti and J. P. Shen, "Exceeding the Dataflow Limit Via Value Prediction," in International Symposium on Microarchitecture, December 1996.
16. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood, "Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation," in International Conference on Programming Language Design and Implementation, June 2005.
17. D. Michie, ""Memo" Functions and Machine Learning," in Nature, April 1968.
18. C. C. Minh et al., "An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees," in International Symposium on Computer Architecture, June 2007.
19. A. Moshovos, G. Memik, A. Choudhary, and B. Falsafi, "JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers," in International Symposium on High-Performance Computer Architecture, January 2001.
20. N. Neelakantam, R. Rajwar, S. Srinivas, U. Srinivasan, and C. Zilles, "Hardware Atomicity for Reliable Software Speculation," in International Symposium on Computer Architecture, June 2007.
21. J.-K. Peir, S.-C. Lai, S.-L. Lu, J. Stark, and K. Lai, "Bloom Filtering Cache Misses for Accurate Data Speculation and Prefetching," in International Conference on Supercomputing, June 2002.
22. M. Postiff, D. Greene, and T. Mudge, "The Store-load Address Table and Speculative Register Promotion," in International Symposium on Microarchitecture, December 2000.
23. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos, "SESC Simulator," January 2005. http://sesc.sourceforge.net.
24. S. Sastry, R. Bodik, and J. Smith, "Characterizing Coarse-Grained Reuse of Computation," in Workshop on Feedback-Directed and Dynamic Optmization, 2000.
25. S. Sethumadhavan, R. Desikan, D. Burger, C Moore, and S. Keckler, "Scalable Hardware Memory Disambiguation for High ILP Processors," in International Symposium on Microarchitecture, December 2003.
26. A. Sodani and G. S. Sohi, "Dynamic Instruction Reuse," in International Symposium on Computer Architecture, June 1997.
27. A. Sodani and G. S. Sohi, "An Empirical Analysis of Instruction Repetition," in International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.
28. G. Sohi, S. Breach, and T. Vijayakumar, "Multiscalar Processors," in International Symposium on Computer Architecture, June 1995.
29. B. Su, S. Habib, W. Zhao, J. Wang, and Y. Wu, "A Study of Pointer Aliasing for Software Pipelining Using Run-time Disambiguation," in International Symposium on Microarchitecture, November 1994.
30. Y. Wu, D.-Y. Chen, and J. Fang, "Better Exploration of Region-level Value Locality with Integrated Computation Reuse and Value Prediction," in International Symposium on Computer Architecture, June 2001.
31. L. Yen et al., "LogTM-SE: Decoupling Hardware Transactional Memory from Caches," in International Symposium on High Performance Computer Architecture, February 2007.