A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 338-341

  Hanson, Scott ^a   Sylvester, Dennis ^a   Blaauw, David ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Gate sizing; Subthreshold circuits; Voltage scaling

Indexed keywords

ENERGY CIRCUITS; ENERGY REDUCTIONS; GATE SIZING; SUBTHRESHOLD CIRCUITS; SUPPLY VOLTAGE SCALING;

BENCHMARKING; CAPACITANCE; ELECTRIC POTENTIAL; ENERGY UTILIZATION; OPTIMIZATION;

ELECTRIC NETWORK ANALYSIS;

EID: 34247274580     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165653     Document Type: Conference Paper

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