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Volumn , Issue , 2008, Pages

Ultra low voltage level shifters to interface sub and super threshold reconfigurable logic cells

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY OF OPERATION; LEVEL SHIFTERS; MULTIPLE-VOLTAGE LEVELS; OPERATING DEVICES; ORDERS-OF-MAGNITUDE; PERFORMANCE REQUIREMENTS; RECONFIGURABLE CIRCUITS; RECONFIGURABLE LOGIC CELLS; SUB-THRESHOLD SIGNALS; SUBTHRESHOLD LOGIC; ULTRA-LOW-POWER; ULTRA-LOW-VOLTAGE; VOLTAGE ISLANDS;

EID: 49349098019     PISSN: 1095323X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AERO.2008.4526473     Document Type: Conference Paper
Times cited : (39)

References (14)
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  • 4
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    • January
    • A. Wang and A. Chandrakasan, "A 180-mV Subthreshold FFT Processor using a Minimum Energy Design Methodology," IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 310-319, January, 2005.
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    • Wang, A.1    Chandrakasan, A.2
  • 5
    • 0028044343 scopus 로고
    • Self-Adjusting Threshold-Voltage Scheme (SATS) for Low Voltage High-Speed Operation
    • May
    • Kobayashi, T.; Sakurai, T., "Self-Adjusting Threshold-Voltage Scheme (SATS) for Low Voltage High-Speed Operation." Custom Integrated Circuits Conf, pp. 271-274, May 1994.
    • (1994) Custom Integrated Circuits Conf , pp. 271-274
    • Kobayashi, T.1    Sakurai, T.2
  • 10
    • 34547348180 scopus 로고    scopus 로고
    • A New Level-up Shifter for High Speed and Wide Range Interface in Ultra Deep Sub-Micron
    • ISCAS
    • Kyoung-Hoi Koo, Jin-Ho Seo, Myeong-Lyong Ko, Jae-Whui Kim : "A New Level-up Shifter for High Speed and Wide Range Interface in Ultra Deep Sub-Micron", IEEE International symposium on Circuits and Systems, 2005. ISCAS 2005, 1063-1065 Vol. 2.
    • (2005) IEEE International symposium on Circuits and Systems , vol.2 , pp. 1063-1065
    • Koo, K.-H.1    Seo, J.-H.2    Ko, M.-L.3    Kim, J.-W.4
  • 12
    • 0036683762 scopus 로고    scopus 로고
    • Low power CMOS level shifters by bootstrapping technique
    • Aug, On pages
    • Tan, S.C. Sun, X.W, "Low power CMOS level shifters by bootstrapping technique", IEEE electronics Letters, Aug 2002, Volume:38, On page(s): 876-878.
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    • Tan, S.C.1    Sun, X.W.2
  • 13
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    • High performance level conversion for dual VDD design
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  • 14
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    • Kanno, Y. Mizuno, H. Tanaka, K. Watanabe, T., Central Res. Lab., Hitachi Ltd., Tokyo; Level Converters With High Immunity to Power-Supply Bouncing for High-Speed Sub-IV LSIs, 2000 symposium onVLSI Circuits Digest of Technical Papers, Publication,date: 2000 On page(s): 202-203.
    • Kanno, Y. Mizuno, H. Tanaka, K. Watanabe, T., Central Res. Lab., Hitachi Ltd., Tokyo; "Level Converters With High Immunity to Power-Supply Bouncing for High-Speed Sub-IV LSIs", 2000 symposium onVLSI Circuits Digest of Technical Papers, Publication,date: 2000 On page(s): 202-203.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.