Investigating crosstalk in sub-threshold circuits

Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Volumn , Issue , 2007, Pages 639-644

  Nanua, Mini ^a   Blaauw, David ^b  

^a SUN MICROSYSTEMS   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS TECHNOLOGY; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ENERGY DISSIPATION; MICROPROCESSOR CHIPS; SENSITIVITY ANALYSIS;

CROSSTALK PROPAGATION; TESTBENCH CIRCUITS;

CIRCUIT THEORY;

EID: 34548120835     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2007.95     Document Type: Conference Paper

References (11)

1. B.H. Calhoun and A. Chandrakasan, "Modeling and Sizing for Minimum Enery Operation in Subthreshold Circuits", IEEE Journal of Solid-State Circuits, Vol. 40, NO. 9, Sep 2005, pp. 1778-1786.
2. S. Hanson et. al., "Ultralow-voltage minimum-energy CMOS", IBM Journal of Research and Developement, Allen Press, Jul./Sep. 2006, pp. 1-22.
3. B.C. Paul, A. Roychowdhury, and K. Roy, "Device Optimization for Ultra-Low Power Digital Sub-Threshold Operation", ISLPED, Aug 2004, pp. 96-101.
4. J. Chen, L.T. Clark, and Y. Cao, "Robust Design of High Fan-In/Out Subthreshold Circuits", IEEE Proceedings ICCD, 2005.
5. M.D. Godfrey, "CMOS Device Modeling for Subthreshold Circuits", IEEE Transactions on Circuits and Systems, Vol. 39,Aug 1992, pp.532-539.
6. F. Caiget, S. Delamas-Bendhia and, E. Sicard, "The Challenge of Signal Integrity in Deep-Submicronmeter CMOS Technology", IEEE Proceedings, Vol. 89, April 200, pp.556-573.
7. P. Heydari and, M. Pedram, "Capacitive Coupling Noise in High-Speed VLSI Circuits", IEEE Transactions CAD, Vol.24, 2005.
8. T. Sakurai, "Closed-Form Expressions for Interconnect Delay, Coupling, and Crosstalk in VLSI's", IEEE Transactions on Electron Devices, Jan 1993, pp. 118-124.
9. K.L. Shepard, "Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits", Transactions IEEE CAD. Vol.18, 1999.
10. R. Levy, et.al., "ClariNet: A Noise analysis tool for deep submicron design", DAC, 2000, pp. 233-238.
11. W. Che, S.K. Gupta and M.A. Breuer, "Analytical Models for Crostalk Excitation and Propagation in VLSI Circuits", IEEE Transactions on CAD of Integrated Circuitsand Systems, Oct 2002, pp. 1117-1131.