Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages

2006 Proceedings - 23rd International VLSI Multilevel Interconnection Conference, VMIC 2006

Volumn , Issue , 2006, Pages 195-202

  Chen, K N ^a   Tsang, C K ^a   Topol, A W ^a   Lee, S H ^b   Furraan, B K ^a   Rath, D L ^a   Lu, J Q ^b   Young, A M ^a   Purushothaman, S ^a   Haensch, W ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATED CIRCUIT; BONDING QUALITY; FABRICATION PROCESS; MANUFACTURABILITY; MANUFACTURING APPLICATIONS; MECHANICAL SUPPORT; STRUCTURAL RELIABILITY; WAFER LEVEL;

INTEGRATED CIRCUITS; THREE DIMENSIONAL; WAFER BONDING;

SEALS;

EID: 84888272824     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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