The design of an SRAM-based field-programmable gate array - Part I: Architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 2, 1999, Pages 191-197

  Chow, Paul ^a,b   Seo, Soon Ong ^c   Rose, Jonathan ^a,b   Chung, Kevin ^d   Páez Monzón, Gerard ^e,f   Rahardja, Immanuel ^g  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c ADVANCED MICRO DEVICES   (United States)

^d XILINX INC   (United States)

^e NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^f UNIVERSIDAD DE LOS ANDES   (Venezuela)

^g Aristo Technology Inc   (United States)

Author keywords

Field programmable gate arrays; FPGA architecture; SRAM programmable

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; RANDOM ACCESS STORAGE;

STATIC RANDOM ACCESS MEMORY (SRAM);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032665576     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.766746     Document Type: Article

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