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Volumn , Issue , 2005, Pages 1875-1878

Placement for the reconfigurable datapath architecture

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC EXPRESSION; DATA FLOW; DATA FLOW GRAPHS; DATA-PATH ARCHITECTURE; GERMANY; GLOBAL INTERCONNECT; HIGH LEVEL DESCRIPTION; HOST COMPUTERS; LOGIC EXPRESSIONS; PROCESSING UNITS; RE-CONFIGURABLE; RECONFIGURABLE COMPUTING; RECONFIGURABLE HARDWARES; RECONFIGURABLE PROCESSING UNITS; SPANNING TREE; UNIVERSITY OF KAISERSLAUTERN;

EID: 36349002781     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464977     Document Type: Conference Paper
Times cited : (7)

References (7)
  • 2
    • 0012733101 scopus 로고    scopus 로고
    • Comparing computing machines
    • John Schewel,editor, Bellingham, WA, November
    • A. DeHon, "Comparing computing machines," in John Schewel,editor, Configurable Computing: Technology aSPIE 3526, Bellingham, WA, November 1998, pp. 124-133.
    • (1998) Configurable Computing: Technology aSPIE 3526 , pp. 124-133
    • DeHon, A.1
  • 4
    • 0029529462 scopus 로고
    • A Datapath Synthesis System for the Reconfigurable Datapath Architecture
    • 95, Nippon Convention Center, Makuhari, Chiba, Japan, Aug. 29, Sept. 1
    • R. W. Hartenstein and R. Kress, "A Datapath Synthesis System for the Reconfigurable Datapath Architecture," Asia and South Pacific Design Automation Conference, ASP-DAC'95, Nippon Convention Center, Makuhari, Chiba, Japan, Aug. 29 - Sept. 1, 1995.
    • (1995) Asia and South Pacific Design Automation Conference, ASP-DAC
    • Hartenstein, R.W.1    Kress, R.2
  • 7
    • 67649091444 scopus 로고    scopus 로고
    • E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R.Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, and A. Sangiovanni-Vincentelli, SIS: A system for sequential circuit synthesis, Electron. Res. Lab. Memo, No. UCB/ERL M92/41, May 1992 R. Sedgewick, Algorithms. Addison Wesley, 1988.
    • E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R.Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, and A. Sangiovanni-Vincentelli, "SIS: A system for sequential circuit synthesis", Electron. Res. Lab. Memo, No. UCB/ERL M92/41, May 1992 R. Sedgewick, Algorithms. Addison Wesley, 1988.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.