Exploiting programmable BIST for the diagnosis of embedded memory cores

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 379-385

  Appello, D ^b   Bernardi, P ^a   Fudoli, A ^b   Rebaudengo, M ^a   Sonza Reorda, M ^a   Tancorre, V ^b   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DESIGN FOR TESTABILITY; STATIC RANDOM ACCESS STORAGE; VLSI CIRCUITS;

EMBEDDED MEMORY CORES;

EMBEDDED SYSTEMS;

EID: 0142215942     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. Y. Zorian, E.J. Marinissen, and S. Dey, Testing embedded-core based system chips, in Proc. International Test Conference, Oct. 1998. pp. 130-143
2. E.J. Marinissen, Y. Zorian, Challenges in Testing Core-based System ICs, IEEE Communications Magazine, Vol. 37, June 1999. pp. 104-109
3. N. Touba, and B. Pouya, Using Partial Isolation Rings to test Core-Based Designs, IEEE Design and Test of Computers, vol. 14, Oct.-Dec. 1997, pp. 52-59
4. S.K. Goel, E.J. Marinissen, Effective and efficient test architecture design for SOCs, in Proc. International Test Conference, Oct. 2002, pp. 529-538
5. E.J. Marinissen, S.K. Goel, M. Lousberg, Wrapper design for embedded core test, in Proc. International Test Conference, Oct. 2000, pp. 911-920
6. T. Bergfeld, D. Niggemeyer, E. Rudnick, Diagnostic testing of embedded memories using BIST, IEEE Conference on Design, Automation and Test in Europe 2000, pp. 305-309
7. C.W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, H.-P. Lin, A Built-in Self Test and Diagnosis Scheme for Embedded SRAM, IEEE Asian Test Symposium, 2000, pp. 45-49
8. H.Kim, Y. Zorian, G. Komoriya, H. Pham, F. Higgins, J. Lewandowski, Built-In Self-Repair for Embedded High Density SRAM, IEEE International Test Conference, 1998, pp.1112-1119
9. A.J. van de Goor, Using March Tests to Test SRAMs, IEEE Design & Test of Computers, Vol. 10, No. 1, pp. 8-14, 1993
10. B.F Cockburn, Tutorial on semiconductor memory testing, Journal of Electronic Testing: Theory and Application, Vol. 5, pp. 321-336, 1994
11. Hetherington et al., Logic BIST for large industrial designs: Real issues and case studies, IEEE International Test Conference, 1999, pp. 358-367
12. C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, T.-Y. Chang, A programmable BIST core for embedded DRAM, IEEE Design and Test of Computers, Vol. 16, No. 1, pp. 59-70, 1999
13. A.J. van de Goor, Testing Semiconductor memories: Theory and Practice, ComTex Publishing, Gouda, The Netherlands, 1998
14. R. Treuer, and V.K. Agarwal, Built-In Self Diagnosis for Repairable Embedded RAMs, IEEE Design and Test of Computers, Vol. 10, No. 2, June 1993, pp. 24-33
15. C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, T.-Y. Chang, A Programmable BIST Core for Embedded DRAM, IEEE Design and Test of Computers, Vol. 16, No. 1, Jan.-March 1999, pp. 59-70
16. C.-H. Tsai, C.-W. Wu, Processor-Programmable Memory BIST for Bus-Connected Embedded Memories, in Proc. Design Automation Conference, 2001, pp. 325-330
17. J. Dreibelbis, J. Barth, H. Kalter, R. Kho, Processor-based Built-In Self-Test for Embedded DRAM, IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, Nov. 1998, pp. 1731-1740
18. P. Bernardi, M. Rebaudengo, M. Sonza Reorda, M. Violante, A P1500-compatible programmable BIST approach for the test of Embedded Flash Memories, Design, Automation and Test in Europe Conference, 2003, pp. 720-725
19. E.J. Marinissen, Y. Zorian, R. Kapur, T. Taylor, L. Whetsel, Towards a Standard for Embedded Core Test: An Example, IEEE International Test Conference, 1999, pp. 616-627
20. D. Appello, F. Corno, M. Giovinetto, M. Rebaudengo, M. Sonza Reorda, A P1500 compliant architecture for BIST-based Diagnosis of embedded RAMs, IEEE Asian Test Symposium, 2001, pp. 97-102
21. D. Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo, M. Sonza Reorda, A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques, IEEE On-Line Testing Workshop, 2002, pp. 112-116