A built-in self-test scheme for soft error rate characterization

Proceedings - 14th IEEE International On-Line Testing Symposium, IOLTS 2008

Volumn , Issue , 2008, Pages 65-70

  Sanyal, Alodeep ^a   Alam, Syed M ^b   Kundu, Sandip ^a  

^a University of Massachusetts   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

Built in self test (BIST); Controllability; Linear feedback shift register (LFSR); Multiple input signature register (MISR); Non concurrent on line BIST; Pseudorandom pattern generator (PRPG); Single event upset (SEU); Soft error rate (SER)

Indexed keywords

BIST DESIGN; BIST SCHEMES; BUILT IN SELF TESTING; BUILT-IN SELF-TEST (BIST); CHIP-LEVEL; CMOS TECHNOLOGIES; CONTROLLABILITY; CURRENT GENERATION; DEVICE OPERATIONS; DEVICE UNDER TESTS; DIAGNOSTIC RESOLUTION; HARDWARE OVERHEADS; LINEAR FEEDBACK SHIFT REGISTER (LFSR); MULTIPLE INPUT SIGNATURE REGISTER (MISR); NON-CONCURRENT ON-LINE BIST; ON-LINE TESTING; PROPOSED ARCHITECTURES; PSEUDORANDOM PATTERN GENERATOR (PRPG); SINGLE EVENT; SINGLE EVENT UPSET (SEU); SOFT ERROR RATE (SER); SOFT ERROR RATES; SOFT ERRORS; SOFT FAILURE; SOFT-ERROR RATE; TEST COST; TEST FAILURE; TIME CONSUMING; TRANSIENT ERRORS;

BUILT-IN SELF TEST; ERROR ANALYSIS; ERROR CORRECTION; ERRORS; HEALTH; IONIZING RADIATION; LEARNING SYSTEMS; MEASUREMENT ERRORS; MICROPROCESSOR CHIPS; TESTING;

ELECTRONIC EQUIPMENT TESTING;

EID: 52049108892     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2008.26     Document Type: Conference Paper

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