Device characteristics of Trigate-FET with barrier constrictions in the channel

Proceedings - 2009 13th International Workshop on Computational Electronics, IWCE 2009

Volumn , Issue , 2009, Pages

  Dehdashti, Nima ^a   Afzalian, A ^a   Lee, C W ^a   Yan, R ^a   Fagas, G ^a   Colinge, J P ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DIRECTION; DEVICE CHARACTERISTICS; DRAIN JUNCTIONS; GATE VOLTAGES; NON EQUILIBRIUM; REAL-SPACE; ROOM TEMPERATURE; TRANSMISSION RESONANCE; TRI-GATE STRUCTURES; TRIGATE; ULTRATHIN SILICON;

ELECTRONICS ENGINEERING; IONIC CONDUCTION;

DRAIN CURRENT;

EID: 70350212719     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWCE.2009.5091103     Document Type: Conference Paper

References (14)

1. S.F. Hu, Y.C. Wu, C.L. Sung et al., "A dual-gate-controlled single-electron transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator nanowire", IEEE Transactions on Nanotechnology, vol. 3, Issue: 1 , pp. 93-97, 2004.
2. M. Saitoh, H. Majima, T. Hiramoto, "Tunneling barrier structures in room-temperature operating silicon single-electron and single-hole transistors", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 42, Issue: 4B, pp. 2426-2428, 2002.
3. B.G. Park, D.H. Kim, K.R. Kim et al., "Single-electron transistors fabricated with sidewall spacer patterning", Superlattices and Microstructures, vol. 34, Issue: 3-6, pp. 231-239, 2003.
4. Boeuf F, Jehl X, Sanquer M et al., "Controlled single-electron effects in nonoverlapped ultra-short silicon field effect transistors", IEEE Ttransactions on Nanotechnology, vol. 2, no. 3, pp. 144-148, 2003.
5. Armin T. Tilke, et. al., "Tunnel Barrier Formation in Silicon Nanowires", Jpn. J. Appl. Phys., Vol. 42, pp. 414-417, 2003.
6. Wang W, Liao JH, Sun JP et al., "Simulation of the electrical characteristics of a one-dimensional quantum dot array", Superlattices and Microstructures, vol. 44, Issue: 6, pp. 721-727, 2008.
7. M. Luisier et al., "Quantum transport in two and three-dimensional nanoscale transistors: Coupled mode effects in the nonequilibrium Green's function formalism", J. Appl. Phys., vol. 100, no. 4, p. 043713, 2006.
8. J. Wang, E. Pollizi and M. Lundstrom, "Three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation", JOURNAL OF APPLIED PHYSICS, vol. 96, Issue: 4, pp. 2192-2203, 2004.
9. A. Martinez et al., "A self-consistent full 3-D real-space NEGF simulator for studying nonperturbative effects in nano-MOSFETs", IEEE Ttransactions on Electron Devices, vol. 54, Issue: 9, pp. 2213-2222, 2007.
10. D. Mamaluy, M. Sabathil, and P. Vogl, "Efficient method for the calculation of ballistic quantum transport", J. Appl. Phys., vol. 93, no. 8, pp. 4628-4633, Apr. 2003.
11. R. Venugopal et al., "Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches", J. Appl. Phys., vol. 92, no. 7, pp. 3730-3739, Oct. 2002.
12. A. Svizhenko, M. P. Anantram, T. R. Govindan, B. Siegel, and R. Venugopal, "Two-dimensional quantum mechanical modeling of nanotransistors", J. Appl. Phys., vol. 91, no. 4, pp. 2343-2354, Feb. 2002.
13. J. Wang, A. Rahman, A. Ghosh, G. Klimeck, and M. Lundstrom, "On the validity of the parabolic effective-mass approximation for the I-V calculation of silicon nanowire transistors", IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1589-1595, Jul. 2005
14. Jin S, Park YJ, Min HS, "A three-dimensional simulation of quantum transport in silicon nanowire transistor in the presence of electron-phonon interactions", Journal of Applied Physics, vol. 99, Issue: 12, 2006.