Single-electron transistors fabricated with sidewall spacer patterning

Superlattices and Microstructures

Volumn 34, Issue 3-6, 2003, Pages 231-239

  Park, Byung Gook ^a   Kim, Dae Hwan ^a   Kim, Kyung Rok ^a   Song, Ki Whan ^a   Lee, Jong Duk ^a  

^a Seoul National University   (South Korea)

Author keywords

Complementary self biasing method; DGSET; MOSET; Multi valued logic; Phase control; Sidewall depletion gate; Sidewall spacer patterning; Single electron transistor; SPICE

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; MOSFET DEVICES; OSCILLATIONS; QUANTUM THEORY; SILICON;

COMPLEMENTARY SELF-BIASING METHOD; DUAL-GATE SINGLE-ELECTRON TRANSISTOR (DGSET); MULTI-VALUED LOGIC; SIDEWALL DEPLETION GATE; SIDEWALL SPACER PATTERNING; SINGLE-ELECTRON TRANSISTOR; SPICE;

ELECTRONS;

EID: 3242685133     PISSN: 07496036     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.spmi.2004.03.013     Document Type: Conference Paper

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