Register placement for low power clock network

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 588-593

  Lu, Yongqiang ^a   Sze, C N ^b   Hong, Xianlong ^a   Zhou, Qiang ^a   Cai, Yici ^a   Huang, Liang ^a   Hu, Jiang ^b  

^a TSINGHUA UNIVERSITY   (China)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTER AIDED DESIGN;

BENCHMARK CIRCUIT; CELL PLACEMENT; CRITICAL PATH DELAYS; LOW POWER CLOCK; POWER PROBLEM; POWER-SUPPLY NOISE; PRESCRIBED SKEW; QUADRATIC PLACEMENT;

LOW POWER ELECTRONICS;

EID: 29144492268     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120971     Document Type: Conference Paper

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