IBM POWER6 microprocessor physical design and design methodology

IBM Journal of Research and Development

Volumn 51, Issue 6, 2007, Pages 685-714

  Berridge, Rex ^a   Averill III, Robert M ^a   Barish, Arnold E ^a   Bowen, Michael A ^a   Camporese, Peter J ^a   DiLullo, Jack ^a   Dudley, Peter E ^a   Keinert, Joachim ^b   Lewis, David W ^a   Morel, Robert D ^a   Rosser, Thomas ^a   Schwartz, Nicole S ^a   Shephard, Philip ^a   Smith, Howard H ^c   Thomas, Dave ^a   Restle, Phillip J ^d   Ripley, John R ^a   Runyon, Stephen L ^a   Williams, Patrick M ^a  

^a IBM   (United States)

^b IBM   (Germany)

^c Thomas J Watson Research Center ^*  (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INFORMATION MANAGEMENT; SOFTWARE DESIGN; TRANSISTORS;

MILLION-TRANSISTOR CHIP; RANDOM LOGIC MACRO;

MICROPROCESSOR CHIPS;

EID: 37549056552     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/rd.516.0685     Document Type: Article

References (2)

1. E. Leobandung, E. Nayakama, H. Mocuta, D. Miyamoto, K. Angyal, M. Meer, H. V. McStay, et al., "High Performance 65 nm SOI Technology with Dual Stress Liner and Low Capacitance SRAM Cell," 2005 Symposium on VLSI Technology, Digest of Technical Papers, June 14-16, 2005, pp. 126-127.
2. J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, and C. J. Anderson, "The Circuit and Physical Design of the POWER4 Microprocessor," IBM J. Res. & Dev. 46, No. 1, pp. 27-51 (2002).