Effects of independent double-gated configuration on polycrystalline-Si nonvolatile memory devices

Applied Physics Letters

Volumn 95, Issue 13, 2009, Pages

  Chen, Wei Chen ^a   Lin, Horng Chih ^a,b   Chang, Yu Chia ^a   Huang, Tiao Yuan ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDITIONAL CONTROL; CONTROL GATES; DOUBLE-GATED CONFIGURATIONS; GATED DEVICES; GATED STRUCTURES; MEMORY DEVICE; NON-VOLATILE MEMORY APPLICATION; NONVOLATILE MEMORY DEVICES; OXIDE NITRIDE OXIDES; POLYCRYSTALLINE-SI; ULTRA-THIN CHANNELS;

NITRIDES; NONVOLATILE STORAGE; THIN FILM TRANSISTORS;

SILICON;

EID: 70349656787     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3238362     Document Type: Article

References (15)

1. J. De Blauwe, IEEE Trans. Nanotechnol. 1536-125X 1, 72 (2002). 10.1109/TNANO.2002.1005428 (Pubitemid 43987437)
2. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, IEEE Electron Device Lett. 0741-3106 21, 543 (2000). 10.1109/55.877205 (Pubitemid 32031234)
3. M. H. White, D. A. Adams, and J. Bu, IEEE Circuits Devices Mag. 8755-3996 16, 22 (2000). 10.1109/101.857747 (Pubitemid 30908243)
4. R. Bez and A. Pirovano, Mater. Sci. Semicond. Process. 1369-8001 7, 349 (2004). 10.1016/j.mssp.2004.09.127
5. B. Yu, X. Sun, S. Ju, D. B. Janes, and M. Meyyappan, IEEE Trans. Nanotechnol. 1536-125X 7, 496 (2008). 10.1109/TNANO.2008.926374
6. J. -W. Han, S. -W. Ryu, C. Kim, S. J. Choi, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y. -K. Choi, Tech. Dig.-Int. Electron Devices Meet. 0163-1918 2007, 929.
7. H. -T. Lue, S. -Y. Wang, E. -K. Lai, Y. -H. Shih, S. -C. Lai, L. -W. Yang, K. -C. Chen, J. Ku, K. -Y. Hsieh, R. Liu, and C. -Y. Lu, Tech. Dig.-Int. Electron Devices Meet. 0163-1918 2005, 547.
8. C. H. Lee, K. I. Choi, M. K. Cho, Y. H. Song, K. C. Park, and K. Kim, Tech. Dig.-Int. Electron Devices Meet. 0163-1918 2003, 613.
9. Y. Fukuzumi, R. Katsumata, M. Kito, M. Kido, M. Sato, H. Tanaka, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, Tech. Dig.-Int. Electron Devices Meet. 0163-1918 2007, 449.
10. R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagatam, L. Zhang, Y. Iwata, R. Kirisawa, H. Aochi, and A. Nitayama, Tech. Dig. VLSI Symp. 2009, 136.
11. J. Fu, N. Singh, K. D. Buddharaju, S. H. G. Teo, C. Shen, Y. Jiang, C. X. Zhu, M. B. Yu, G. Q. Lo, N. Balasubramanian, D. L. Kwong, E. Gnani, and G. Baccarani, IEEE Electron Device Lett. 0741-3106 29, 518 (2008). 10.1109/LED.2008.920267 (Pubitemid 351676327)
12. H. C. Lin, M. H. Lee, C. J. Su, T. Y. Huang, C. C. Lee, and Y. S. Yang, IEEE Electron Device Lett. 0741-3106 26, 643 (2005). 10.1109/LED.2005.853669 (Pubitemid 41430955)
13. H. C. Lin, H. H. Hsu, C. J. Su, and T. Y. Huang, IEEE Electron Device Lett. 0741-3106 29, 718 (2008). 10.1109/LED.2008.2000654
14. H. C. Lin, W. C. Chen, C. D. Lin, and T. Y. Huang, IEEE Electron Device Lett. 0741-3106 30, 644 (2009). 10.1109/LED.2009.2018493
15. S. -K. Sung, S. -H. Lee, B. Y. Choi, J. J. Lee, J. -D. Choe, E. S. Cho, Y. J. Ahn, D. Choi, C. -H. Lee, D. H. Kim, Y. -S. Lee, S. B. Kim, D. Park, and B. -I. Ryu, Tech. Dig. VLSI Symp. 2006, 86. 10.1109/VLSIT.2006.1705229