Si-nanowire based gate-all-around nonvolatile SONOS memory cell

IEEE Electron Device Letters

Volumn 29, Issue 5, 2008, Pages 518-521

  Fu, J ^a,b   Singh, N ^a   Buddharaju, K D ^a   Teo, S H G ^a   Shen, C ^b   Jiang, Y ^a,b   Zhu, C X ^b   Yu, M B ^a   Lo, G Q ^a   Balasubramanian, N ^a   Kwong, D L ^a   Gnani, E ^c   Baccarani, G ^c  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Gate all around (GAA); Nanowire (NW); Nonvolatile memory (NVM); Silicon oxide nitride oxide silicon (SONOS)

Indexed keywords

ELECTRIC FIELDS; ELECTRON TUNNELING; NANOWIRES; NONVOLATILE STORAGE; SEMICONDUCTOR DEVICE MANUFACTURE; THRESHOLD VOLTAGE;

GATE-ALL-AROUND; NONVOLATILE MEMORY; SILICON-OXIDE-NITRIDE-OXIDE-SILICON;

FLASH MEMORY;

EID: 43549116120     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.920267     Document Type: Article

References (10)

1. J. D. Lee, S. H. Hur, and J. D. Choi, "Effects of floating-gate interference on NAND flash memory cell operation," IEEE Electron Device Lett., vol. 23, no. 5, pp. 264-266, May 2002.
2. International Technology Roadmap for Semiconductors, 2006.
3. M. H. White, D. A. Adams, and J. Bu, "On the go with SONOS," IEEE Circuits Devices Mag., vol. 16, no. 4, pp. 22-31, Jul. 2000.
4. M. Saitoh, E. Nagata, and T. Hiramoto, "Effects of ultra-narrow channel on characteristics of MOSFET memory with silicon nanocrystal floating gates," in IEDM Tech. Dig., 2002, pp. 181-184.
5. P. Xuan, M. She, B. Harteneck A. Liddle, J. Bokor, and T. J. King, "FinFET SONOS flash memory for embedded applications," in IEDM Tech. Dig., 2003, pp. 609-612.
6. E. Gnani, S. Reggiani, M. Rudan, and G. Baccarani, "Design considerations and comparative investigation of ultra-thin SOI, double-gate and cylindrical nanowire FETs," in Proc. IEEE ESSDERC 2006, pp. 371-374.
7. S. D. Suk, K. H. Yeo, K. H. Cho, M. Li, Y. Y. Yeoh, K. H. Hong, S. H. Kim, Y. H. Koh, S. G. Jung, W. J. Jang, D. W. Kim, D. G. Park, and B. I. Ryu. "Gate-all-around twin silicon nanowire SONOS memory," in VLSI Symp. Tech. Dig., 2007, pp. 142-143.
8. N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K. M. Hoe, S. R. Omampuliyur, D. Tripathi, A. O. Adeyeye, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance," in IEDM Tech. Dig., 2006, pp. 547-550.
9. H. J. Lee, S. W. Ryu, J. W. Han, L. E. Yu, M. Im, C. Kim, E. Lee, K. H. Kim, J. H. Kim, D. Bae, S. C. Jeon, K. H. Kim, G. S. Lee, J. S. Oh, Y. C. Park, W. H. Bae, J. J. Yoo, J. M. Yang, H. M. Lee, and Y. K. Choi, "A nanowire transistor for high performance logic and terabit non-volatile memory devices," in VLSI Symp. Tech. Dig., 2007, pp. 144-145.
10. T.-H. Hsu, H.-T. Lue, E.-K. Lai, J.-Y. Hsien, S.-Y. Wang, L.-W. Yang, Y.-C. King, T. Yang, K.-C. Chen, K.-Y. Hsieh R. Liu, and C.-Y. Lu, "A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET." in IEDM Tech. Dig., 2007, pp. 913-916.