Performance enhancement in double-gated poly-Si nanowire transistors with reduced nanowire channel thickness

IEEE Electron Device Letters

Volumn 30, Issue 6, 2009, Pages 644-646

  Lin, Horng Chih ^a,b   Chen, Wei Chen ^a   Huang, Tiao Yuan ^a   Lin, Chuan Ding ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

Double gate; Nanowire (NW); Polycrystalline silicon (poly Si)

Indexed keywords

CHANNEL THICKNESS; CONDUCTION CHANNEL; CONDUCTION MECHANISM; DEVICE OPERATIONS; DOUBLE GATE; NANOWIRE TRANSISTORS; PERFORMANCE ENHANCEMENTS; POLY-SI; POLYCRYSTALLINE SILICON (POLY-SI);

NANOWIRES;

POLYSILICON;

EID: 67649382027     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2018493     Document Type: Article

References (10)

1. M. Im, J.-W. Han, H. Lee, L.-E. Yu, S. Kim, S. C. Jeon, K. H. Kim, G. S. Lee, J. S. Oh, Y. C. Park, H. M. Lee, and Y.-K. Choi, "Multiple-gate CMOS thin-film transistor with polysilicon nanowire," IEEE Electron Device Lett., vol. 29, no. 1, pp. 102-105, Jan. 2008.
2. H. Yin, W. Xianyu, A. Tikhonovsky, and Y. S. Park, "Scalable 3-D fin-like poly-Si TFT and its nonvolatile memory application," IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 578-584, Feb. 2008.
3. H. C. Lin, M. H. Lee, C. J. Su, T. Y. Huang, C. C. Lee, and Y. S. Yang, "A simple and low-cost method to fabrication TFTs with poly-Si nanowire channel," IEEE Electron Device Lett., vol. 26, no. 9, pp. 643-645, Sep. 2005.
4. H. C. Lin, M. H. Lee, C. J. Su, and S. W. Shen, "Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels," IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2471-2477, Oct. 2006.
5. H. C. Lin, H. H. Hsu, C. J. Su, and T. Y. Huang, "A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate," IEEE Electron Device Lett., vol. 29, no. 7, pp. 718-720, Jul. 2008.
6. J. P. Colinge, A. J. Quinn, L. Floyd, G. Redmond, J. C. Alderman, W. Xiong, C. R. Cleavelin, T. Schulz, K. Schruefer, G. Knoblinger, and P. Patruno, "Low-temperature electron mobility in trigate SOI MOSFETs," IEEE Electron Device Lett., vol. 27, no. 2, pp. 120-122, Feb. 2006.
7. D. Hisamoto, W. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asana, T. King, J. Bokor, and C. Hu, "A folded channel MOSFET for deep-subtenth micron era," in IEDM Tech. Dig., 1998, pp. 1032-1034.
8. H. H. Hsu, H. C. Lin, L. Chan, and T. Y. Huang, "Threshold voltage fluctuation of double-gated poly-Si nanowire field-effect transistor," IEEE Electron Device Lett., vol. 30, no. 3, pp. 243-245, Mar. 2009.
9. A. López-Villanueva, P. Cartujo-Cassinello, F. Gámiz, J. Banqueri, and A. J. Palma, "Effects of the inversion-layer centroid on the performance of double-gate MOSFETs," IEEE Trans. Electron Devices vol. 47, no. 1, pp. 141-146, Jan. 2000.
10. T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono, Y. Takahashi, and K. Murase, "Ultimately thin double-gate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 830-838, Mar. 2003.