A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse - T gate

IEEE Electron Device Letters

Volumn 29, Issue 7, 2008, Pages 718-720

  Lin, Horng Chih ^a   Hsu, Hsing Hui ^a   Su, Chun Jung ^a   Huang, Tiao Yuan ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Field effect transistor; Multiple gate (MG); Nanowire (NW); Poly Si

Indexed keywords

ELECTRIC WIRE; INVERSE PROBLEMS; NANOSTRUCTURED MATERIALS; NANOSTRUCTURES; NANOWIRES; NONMETALS; OPTICAL DESIGN; POLYSILICON; SILICON;

DEVICE OPERATIONS; ETCHING TECHNIQUES; GATE BIASES; GATE OPERATIONS; MULTIPLE GATE; NANO WIRES; PERFORMANCE ENHANCEMENTS; POLY-SI; POLYCRYSTALLINE SILICON (P-SI); PROCESS FLOWS; SUBTHRESHOLD SWING (SS); TOP GATE (TG);

FIELD EFFECT TRANSISTORS;

EID: 47249092862     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2000654     Document Type: Article

References (10)

1. H. C. Lin, M. H. Lee, C. J. Su, T. Y. Huang, C. C. Lee, and Y. S. Yang, "A simple and low-cost method to fabrication TFTs with poly-Si nanowire channel," IEEE Electron Device Lett., vol. 26, no. 9, pp. 643-645, Sep. 2005.
2. H. C. Lin, M. H. Lee, C. J. Su, and S. W. Shen, "Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels," IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2471-2477, Oct. 2006.
3. H. C. Lin and C. J. Su, "High-performance poly-Si nanowire NMOS transistors," IEEE Trans. Nanotechnol., vol. 6, no. 2, pp. 206-212, Mar. 2007.
4. D. Hisamoto, W. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asana, T. King, J. Bokor, and C. Hu, "A folded channel MOSFET for deep-subtenth micron era," in IEDM Tech. Dig., 1998, pp. 1032-1034.
5. J. P. Colinge, A. J. Quinn, L. Floyd, G. Redmond, J. C. Alderman, W. Xiong, C. R. Cleavelin, T. Schulz, K. Schruefer, G. Knoblinger, and P. Patruno, "Low-temperature electron mobility in trigate SOI MOSFETs," IEEE Electron Device Lett., vol. 27, no. 2, pp. 120-122, Feb. 2006.
6. S. D. Suk, S. Y. Lee, S. M. Kim, E. J. Yoon, M. S. Kim, M. Li, C. W. Oh, K. H. Yeo, S. H. Kim, D. S. Shin, K. H. Lee, H. S. Park, J. N. Han, C. J. Park, J. B. Park, D.W. Kim, D. Park, and B. I. Ryu, "High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability," in IEDM Tech. Dig., 2005, pp. 735-738.
7. M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike, and E. Suzuki, "Demonstration, analysis and device design considerations for independent double-gate MOSFETS," IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2046-2053, Sep. 2005.
8. F. J. García Ruiz, A. Godoy, F. Gámiz, C. Sampedro, and L. Donetti, "A comprehensive study of the corner effects in Pi-Gate MOSFETs including quantum effects," IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3369-3377, Dec. 2007.
9. M. Im, J.-W. Han, H. Lee, L.-E. Yu, S. Kim, S. C. Jeon, K. H. Kim, G. S. Lee, J. S. Oh, Y. C. Park, H. M. Lee, and Y.-K. Choi, "Multiple-gate CMOS thin-film transistor with polysilicon nanowire," IEEE Electron Device Lett., vol. 29, no. 1, pp. 102-104, Jan. 2008.
10. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance," IEEE Electron Device Lett., vol. EDL-8, no. 9, pp. 410-412, Sep. 1987.