Experimental verification of scan-architecture-based evaluation technique of SET and SEU soft-error rates at each flip-flop in logic VLSI systems

IEEE Transactions on Nuclear Science

Volumn 56, Issue 4, 2009, Pages 1958-1963

  Yanagawa, Y ^a   Kobayashi, D ^b,c   Hirose, K ^b,c   Makino, T ^c   Saito, H ^a,b   Ikeda, H ^b,c   Onoda, S ^d   Hirao, T ^d   Ohshima, T ^d  

^a UNIVERSITY OF TOKYO   (Japan)

^b JAPAN AEROSPACE EXPLORATION AGENCY   (Japan)

^c GRADUATE UNIVERSITY FOR ADVANCED STUDIES   (Japan)

^d JAPAN ATOMIC ENERGY AGENCY   (Japan)

Author keywords

Integrated circuit radiation effects; Irradiation test; Logic VLSI system; Scan architecture; Single event transient; Single event upset

Indexed keywords

INTEGRATED CIRCUIT RADIATION EFFECTS; IRRADIATION TEST; LOGIC VLSI SYSTEM; SCAN ARCHITECTURE; SINGLE EVENT TRANSIENT; SINGLE EVENT UPSET;

ARCHITECTURAL DESIGN; CELL MEMBRANES; COSINE TRANSFORMS; ELECTRIC BATTERIES; ELECTRIC NETWORK ANALYSIS; ERROR CORRECTION; INTEGRATED CIRCUITS; IRRADIATION; LOGIC DEVICES; MICROPROCESSOR CHIPS; RADIATION EFFECTS; TESTING; TRANSIENTS; URANIUM POWDER METALLURGY;

LOGIC CIRCUITS;

EID: 69549111409     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2009.2020166     Document Type: Conference Paper

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