Scan-architecture-based evaluation technique of SET and SED soft-error rates at each flip-flop in logic VLSI systems

Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS

Volumn , Issue , 2007, Pages

  Yanagawa, Y ^a   Kobayashi, D ^b   Ikeda, H ^b   Saito, H ^a,c   Hirose, K ^b  

^a UNIVERSITY OF TOKYO   (Japan)

^b JAPAN AEROSPACE EXPLORATION AGENCY   (Japan)

^c GRADUATE UNIVERSITY FOR ADVANCED STUDIES   (Japan)

Author keywords

Integrated circuit radiation effects; Irradiation test; Logic VLSI system; Scan architecture; Single event transient; Single event upset

Indexed keywords

INTEGRATED CIRCUIT RADIATION EFFECTS; IRRADIATION TEST; LOGIC VLSI SYSTEM; SCAN ARCHITECTURE; SINGLE EVENT TRANSIENT; SINGLE EVENT UPSET;

COSINE TRANSFORMS; ELECTRIC BATTERIES; ELECTRIC NETWORK ANALYSIS; ERROR CORRECTION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUITS; IRRADIATION; RADIATION EFFECTS; TRANSIENTS; URANIUM POWDER METALLURGY;

LOGIC CIRCUITS;

EID: 70449602547     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RADECS.2007.5205569     Document Type: Conference Paper

References (14)

1. H. Nguyen, Y. Yagil, N. Seifert, and M. Reitsma, "Chip-level soft error estimation method," IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 365-381, Sep. 2005.
2. S. Funatsu, N. Wakatsuki, and T. Arima, "Test generation systems in Japan," in Proc. the 12th Conference on Design Automation (DAC '75), Piscataway, NJ, USA, 1975, pp. 114-122.
3. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. Hoboken, NJ: Wiley, 1993.
4. N. H. E. Weste and D. Harris, CMOS VLSI Design, 3rd ed. Boston, MA: Addison-Wesley, 2005.
5. R. Kuppuswamy, P. DesRosier., D. Feltham, R. Sheikh, and P. Thadikaran, "Full hold-scan systems in microprocessors: Cost/benefit analysis," Intel Technology Journal, vol. 8, no. 1, pp. 63-72, Feb. 2004.
6. D. C. Pham, T. Aipperspach, D. Boerstler, M. Bolliger, R. Chaudhry, D. Cox, P. Harvey, P. M. Harvey, H. P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Pham, J. Pille, S. Posluszny, M. Riley, D. L. Stasiak, M. Suzuoki, O. Takahashi, J. Warnock, S. Weitzel, D. Wendel, and K. Yazawa, "Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor," IEEE J. Solid-Stale Circuits, vol. 41, no. 1, pp. 179-196, Jan. 2006.
7. N. Tendolkar, D. Belete, A. Razdan, H. Reyes, B. Schwarz, and M. Sullivan, "Test methodology for Freescale's high performance e600 core based on PowerPC® instruction set architecture," in Proc. IEEE International Test Conference (ITC'05), Nov. 2005.
8. S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, "Robust system design with built-in soft-error resilience," IEEE Computer, vol. 38, no. 2, pp. 43-52, Feb. 2005.
9. S. Buchner, M. Baze, D. Brown, D. McMorrow, and J. Melinger, "Comparison of error rates in combinational and sequential logic," IEEE Trans. Nucl. Sci., vol. 44., no. 6, pp. 2209-2216, Dec. 1997.
10. P. E. Dodd, M. R. Shaneyfelt, J. A. Felix, and J. R. Schwank, "Production and propagation of single-event transients in high-speed digital logic ICs," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3278-3284, Dec. 2004.
11. P. Eaton., J. Benedetto, D. Mavis, K. Avery, M. Sibley, M. Gadlage, and T. Turflinger, "Single event transient pulse width measurements using a variable temporal latch technique," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3365-3368, Dec. 2004.
12. J.M. Benedetto, P. H. Eaton, D. G. Mavis, M. Gadlage, and T.Turflinger, "Digital single event transient trends with technology node scaling," IEEE Trans. Nucl. Sci., vol. 53, no. 6., pp. 3462-3465, Dec. 2006.
13. T. Calin, M. Nicolaidis, and R Velazco,"Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, no. 6t pp. 2874-2878, Dec. 1996.
14. K. Hirose, H. Saito, Y. Kuroda, S. Ishii, Y. Fukuoka, and D. Takahashi, "SEU resistance in advanced SOI-SRAMs fabricated by commercial technology using a rad-hard circuit design," IEEE Trans. Nucl. Sci., vol. 49, no. 6, pp. 2965-2968, Dec. 2002.