Scan-architecture-based evaluation technique of SET and SEU soft-error rates at each flip-flop in logic VLSI systems

IEEE Transactions on Nuclear Science

Volumn 55, Issue 4, 2008, Pages 1947-1952

  Yanagawa, Yoshimitsu ^a   Kobayashi, Daisuke ^b,c   Ikeda, Hirokazu ^b,c   Saito, Hirobumi ^a,d   Hirose, Kazuyuki ^b,c  

^a UNIVERSITY OF TOKYO   (Japan)

^b JAPAN AEROSPACE EXPLORATION AGENCY   (Japan)

^c GRADUATE UNIVERSITY FOR ADVANCED STUDIES   (Japan)

^d JAPAN AEROSPACE EXPLORATION AGENCY   (Japan)

Author keywords

Integrated circuit radiation effects; Irradiation test; Logic VLSI system; Scan architecture; Single event transient; Single event upset

Indexed keywords

ELECTRIC BATTERIES; ERROR ANALYSIS; ERROR CORRECTION; ERRORS; FLIP FLOP CIRCUITS; LEARNING SYSTEMS; SILICON;

INTEGRATED CIRCUIT RADIATION EFFECTS; IRRADIATION TEST; LOGIC VLSI SYSTEM; SCAN ARCHITECTURE; SINGLE EVENT TRANSIENT; SINGLE EVENT UPSET;

TRANSIENTS;

EID: 53349171492     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2008.2000772     Document Type: Conference Paper

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