Electroplated metal buried interconnect and through-wafer metal-filled via technology for high-power integrated electronics

IEEE Transactions on Advanced Packaging

Volumn 32, Issue 3, 2009, Pages 695-702

  Ji, Chang Hyeon ^a   Herrault, Florian ^a   Hopper, Peter ^b   Smeys, Peter ^b   Johnson, Peter ^b   Allen, Mark G ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

Electroplated metal; Interconnection; Spray coating; Through wafer via

Indexed keywords

ANALYTICAL CALCULATION; BONDING PROCESS; BOTTOM SURFACES; CHAIN STRUCTURE; DEEP TRENCH; ELECTRICAL INTEGRITY; ELECTROPLATED COPPER; ELECTROPLATED METAL; ELECTROPLATED METALS; FABRICATION PROCESS; FLIP CHIP; HIGH POWER APPLICATIONS; HIGH VOLTAGE TRANSISTOR; HIGH-DENSITY ARRAYS; HIGH-POWER; HOLE FILLING PROCESS; INTEGRATED ELECTRONICS; INTERCONNECT STRUCTURES; INTERCONNECTION; LOW RESISTANCE; MICRO-ELECTRONIC DEVICES; RESISTANCE TESTING; SILICON SUBSTRATES; SPRAY COATING; TEST STRUCTURE; THROUGH-WAFER VIA; THROUGH-WAFER VIAS; VIA TECHNOLOGIES; VOID-FREE;

CHIP SCALE PACKAGES; DC GENERATORS; ELECTRIC POTENTIAL; ELECTROPLATING; FABRICATION; METALS; PHOTORESISTORS; PHOTORESISTS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; SUBSTRATES; SURFACE TREATMENT;

WAFER BONDING;

EID: 68949188123     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2008.2010713     Document Type: Article

References (15)

1. A. Polyakov,T. Grob, R. A. Hovenkamp, H. J. Kettelarij, I. Eidner, M. A. de Samber, M. Bartek, and J. N. Burghartz, "Comparison of via-fabrication techniques for through-wafer electrical interconnect applications," in Electron. Compon.Technol. Conf.Tech. Digest, 2004, pp. 1466-1470.
2. Z. Wang, L. Wang, N. T. Nguyen, W. A. H. Wien, and H. Schellevis, "Silicon micromachining of high aspect ratio high-density through-wafer electrical interconnects for 3-D multichip packaging," IEEE Trans. Adv. Packag., vol. 29, no. 3, pp. 615-622, Sep. 2006.
3. N. Ranganathan, J. Ning, L. Ebin, C. S. Premachandran, K. Prasad, and N. Balasubramanian, "Through-wafer interconnection by deep damascene process for MEMS and 3D wafer level packaging," in Electron. Packag. Technol. Conf. Tech. Digest, 2005, pp. 238-242.
4. J. H.Wu, J. Scholvin, and J. A. del Alamo, "A through-wafer interconnect in silicon for RFICs," IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1765-1771, Nov. 2004.
5. A. A. Ayón, R. Braff, C. C. Lin, H. H. Sawin, and M. A. Schmidt, "Characterization of a time multiplexed inductively coupled plasma etcher," J. Electrochem. Soc., vol. 146, no. 1, pp. 339-349, 1999.
6. S. Spiesshoefer, J. Patel, T. Lam, L. Cai, S. Polamreddy, R. F. Figueroa, S. L. Burkett, L. Schaper, R. Geil, and B. Rogers, "Copper electroplating to fill blind vias for three-dimensional integration," J. Vac. Sci. Technol. A., vol. 24, no. 4, pp. 1277-1282, 2006.
7. K. Kondo, T. Yonezawa, D. Mikami, T. Okubo, Y. Taguchi, K. Takahashi, and D. P. Barkey, "High-aspect-ratio copper-via-filling for three-dimensional chip stacking; II. Reduced electrodeposition process time," J. Electrochem. Soc., vol. 152, no. 11, pp. H173-177, 2005.
8. J.-H. Park, H.-C. Lee, Y.-H. Park, Y.-D. Kim, C.-H. Ji, J. Bu, and H.-J. Nam, "A fully wafer-level packaged RF MEMS switch with low actuation voltage using a piezoelectric actuator," J. Micromech. Microeng., vol. 16, pp. 2281-2286, 2006.
9. C.-H. Ji, F. Herrault, and M. G. Allen, "Metal buried interconnect process for through-wafer interconnection," J. Micromech. Microeng. vol. 18, p. 085016, 2008.
10. U.-B. Kang and Y.-H. Kim, "Electrical characteristics of fine pitch flip chip solder joints fabricated using low temperature solders," in Tech. Digest, Electron. Compon. Technol. Conf., 2004, pp. 1952-1958.
11. S. K. Pienimaa, J. Miettinen, and E. Ristolainen, "Stacked modular package," IEEE Trans. Adv. Packag., vol. 27, no. 3, pp. 461-466, Sep. 2004.
12. N. P. Pham, E. Boellaard, J. N. Burghartz, and P. M. Sarro, "Photoresist coating methods for the integration of novel 3-D RF microstructures," J. Microelectromech. Syst., vol. 12, pp. 491-499, 2004.
13. K. Fischer and R. Süss, "Spray coating A solution for resist film deposition across severe topography," in IEEE/SEMI Int. Electron. Manufacturing Technol. Symp., 2004, pp. 338-341.
14. D. P. Arnold, F. Cros, I. Zana, D. Veazie, and M. G. Allen, "Electroplated metal microstructures embedded in fusion-bonded silicon: Conductors and magnetic materials," J. Microelectromech. Syst., vol. 13, no. 5, pp. 791-798, 2004.
15. F. Herrault, C.-H. Ji, S. Rajaraman, R. H. Shafer, and M. G. Allen, "Electrodeposited metal structures in high aspect ratio cavities using vapor deposited polymer molds and laser micromachining," in 14th Int. Conf. Solid-State Sensors, Actuators Microsyst., 2007, pp. 513-516.