Through-wafer interconnection by deep damascene process for MEMS and 3D wafer level packaging

Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005

Volumn 1, Issue , 2005, Pages 238-242

  Ranganathan, N ^a   Ning, Jiang ^a   Ebin, Liao ^a   Premachandran, C S ^a   Prasad, K ^b   Balasubramanian, N ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; ELECTROPLATING; MICROELECTROMECHANICAL DEVICES; PLASMA ETCHING; SILICON WAFERS; THERMAL STRESS;

COMB STRUCTURE; SILICON COPPER; VOLTAGE STRESSES;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 33847328761     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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11. th Electronic Components and Technology Conference, Orlando, Florida (USA), May 31- June 3, 2005, pp 343-348.