Impact of gate leakage on performances of phase-locked loop circuit in nanoscale CMOS technology

IEEE Transactions on Electron Devices

Volumn 56, Issue 8, 2009, Pages 1774-1779

  Chen, Jung Sheng ^a   Ker, Ming Dou ^b,c  

^a FAIRCHILD SEMICONDUCTOR   (United States)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c I SHOU UNIVERSITY   (Taiwan)

Author keywords

Gate tunneling leakage; Loop filter; MOS capacitor; Phase locked loop (PLL)

Indexed keywords

CIRCUIT PERFORMANCE; CMOS PROCESSS; GATE LEAKAGES; GATE-TUNNELING LEAKAGE; LOOP FILTER; NANOSCALE CMOS; OXIDE THICKNESS; PERFORMANCE DEGRADATION; PHASE-LOCKED LOOP (PLL); SECOND ORDERS; STATIC PHASE ERRORS; THIN GATE OXIDES; TUNNELING LEAKAGE;

CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; JITTER; NANOSTRUCTURED MATERIALS; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; TUNNELING (EXCAVATION); WIND TUNNELS;

MOS CAPACITORS;

EID: 68349127368     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2022696     Document Type: Article

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