A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Lin, Jerry ^a   Haroun, Baher ^a   Foo, Tim ^a   Wang, Jin Sheng ^a   Helmick, Bob ^a   Randall, Scott ^a   Mayhugh, Terry ^a   Barr, Chris ^a   Kirkpatrick, Jeff ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MICROGRAPH; DIGITALLY CONTROLLED OSCILLATOR; LOGARITHMIC TIME DIGITIZER;

BANDWIDTH; CALIBRATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; FREQUENCIES; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; TRANSFER FUNCTIONS;

CMOS INTEGRATED CIRCUITS;

EID: 2442649398     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. J. Maneatis et al.,"Self-Biased High-Bandwidth Low Jitter 1-to-4096 Multiplier Clock-Generator PLL," ISSCC Dig. Tech. Papers, pp.424-425, Feb. 2003.
2. B. Razavi, "Design of Analog Integrated Circuits," p. 515, McGraw-Hill, 2001.