SCOPUS 정보 검색 플랫폼

Volumn , Issue , 2007, Pages 664-665

Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; JITTER; LEAKAGE CURRENTS; MOS CAPACITORS;

GATE TUNNELING LEAKAGE; SECOND-ORDER LOOP FILTER; STATIC PHASE ERROR;

PHASE LOCKED LOOPS;

EID: 34548781895 PISSN: 00999512 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/RELPHY.2007.370002 Document Type: Conference Paper

Times cited : (2)

References (8)

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- Lee, W.-C.¹ Hu, C.²

2
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- BSIM4 gate leakage model including source-drain partition
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3
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- A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO
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- (2001) Proc. IEEE Custom Integrated Circuits Conf , pp. 213-216
- Minami, K.¹ Fukaishi, M.² Mizuno, M.³ Onishi, H.⁴ Noda, K.⁵ Imai, K.⁶ Horiuchi, T.⁷ Yamaguchi, H.⁸ Sato, T.⁹ Nakamura, K.¹⁰ Yamashina, M.¹¹

4
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- A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz
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- (2002) IEEE Int. Solid-State Circuits Conf Dig. Tech. Papers , pp. 272-274
- Holzer, R.¹

7
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- A 1-4 Gbps quad transceiver cell using PLL with gate current leakage compensator in 90nm CMOS
- Y. Frans, N. Nguyen, B. Daly, Y. Wang, D. Kim, T. Bystrom, D. Olarte, and K. Donnelly, "A 1-4 Gbps quad transceiver cell using PLL with gate current leakage compensator in 90nm CMOS," in Proc. IEEE Int. Symp. VLSI Circuits, 2004, pp. 134-137.
- (2004) Proc. IEEE Int. Symp. VLSI Circuits , pp. 134-137
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8
- 0003510261
- NJ: Prentice Hall
- D. H. Wolaver, Phase-Locked Loop Circuit Design. NJ: Prentice Hall, 1991.
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