A gate leakage reduction strategy for future CMOS circuits

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 317-320

  Draždžiulis, Mindaugas ^a   Larsson Edefors, Per ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS OF MECHANISMS; CMOS CIRCUITS; GATE LEAKAGE REDUCTION; GATE LEAKAGES; INPUT PATTERNS; SUB-THRESHOLD LEAKAGE; TUNNELLING CURRENT; TWO-INPUT NAND GATES;

CMOS INTEGRATED CIRCUITS;

LEAKAGE CURRENTS;

EID: 84893773446     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257136     Document Type: Conference Paper

References (7)

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2. N. Yang et al., "A Comparative Study of Gate Di-rect Tunneling and Drain Leakage Currents in N-MOSFET's With Sub-2nm Gate Oxides, " IEEE Transactions on ED, vol. 47, no. 8, pp. 1636-1644, Aug. 2000.
3. Ying Shi et al., "Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFETs, " IEEE Transac-tions on ED, vol. 45, no. 11, pp. 2355-2360, Nov. 1998.
4. Chang-Hoon Choi et al., "Impact of Gate Direct Tun-neling Current on Circuit Performance: a Simulation Study, " IEEE Transactions on ED, vol. 48, no. 12, pp. 2823-2829, Dec. 2001.
5. K. N. Yang et al., "Characterization and Modeling of Edge Direct Tunneling (EDT) Leakage in Ultrathin Gate Oxide MOSFET's, " IEEE Transactions on ED, vol. 48, no. 6, pp. 1159-1164, June 2001.
6. K. M. Cao et al., "BSIM4 Gate Leakage Model In-cluding Source-Drain Partition, " in IEDM Technical Digest, IEDM, 2000, pp. 815-818.
7. Kyeong-Sik Min et al., "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era, " in Digest of Technical Papers, ISSCC, 2003, pp. 400-402.