A 1-4 Gbps quad transceiver cell using PLL with gate current leakage compensator in 90nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 134-137

  Frans, Yohan ^a   Nguyen, Nhat ^a   Daly, Barry ^a   Wang, Yueyong ^a   Kim, Dennis ^a   Bystrom, Todd ^a   Olarte, Dennis ^a   Donnelly, Kevin ^a  

^a RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DATA TRANSFER; ERROR COMPENSATION; FUEL CELLS; GATES (TRANSISTOR); LEAKAGE CURRENTS; MAGNETIC FILTERS; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; SYNCHRONIZATION; TELECOMMUNICATION NETWORKS;

COMPENSATORS; DATA TRANSITION; LOOP-FILTER CAPACITANCE; TRANSMIT CLOCK JITTERS;

TRANSCEIVERS;

EID: 4544245195     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsic.2004.1346534     Document Type: Conference Paper

References (6)

1. K. Chang, et. al., "A 0.4-4Gb/s CMOS Quad Transceiver Cell using On-chip Regulated Dual-Loop PLLs", VLSI Circuit Symposium, 2002.
2. S. Sidiropoulos, et.al., "Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers", VLSI Circuit Symposium, 2000.
3. R. Holzer, "A 1V CMOS PLL Designed in High-Leakage CMOS Process Operating at 10-700MHz", ISSCC 2002.
4. S. Sidiropulos, et.al., "A semi-digital DLL", IEEE JSSCC, Nov. 2000.
5. T. Lee, et.al., "A 2.5V CMOS Delay-Locked Loop for an 18 Mbit, 500MB/s DRAM", IEEE JSSCC, Dec. 1994.
6. A. Fiedler, et.al., "A 1.0625Gb/s Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis", ISSCC, 1997.