Automatic scaling procedures for analog design reuse

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 12, 2006, Pages 2539-2547

  Savio, Alessandro ^a   Colalongo, Luigi ^a   Quarantelli, Michele ^b   Kovács Vajna, Zolt M ^a  

^a UNIVERSITY OF BRESCIA   (Italy)

^b PDF Solutions Italia   (Italy)

Author keywords

Analog integrated circuits; Design automation; MOSFET; Technology CAD

Indexed keywords

ASPECT RATIO; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC CONDUCTANCE; MOSFET DEVICES; TRANSCONDUCTANCE;

ANALOG DESIGN REUSE; ANALOG INTEGRATED CIRCUITS; AUTOMATIC SCALING; DESIGN AUTOMATION;

ELECTRIC NETWORK TOPOLOGY;

EID: 33845752084     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.883849     Document Type: Article

References (11)

1. C. Galup-Montoro and M. C. Schneider, "Resizing rules for the reuse of MOS analog designs," in Proc. XIII Symp. Integr. Circuits Syst. Design (SBCCI'00), Manaos, Brazil, Sep. 2000, pp. 89-93.
2. C. Galup-Montoro, M. Schneider, and R. M. Coitinho, "Resizing rules for MOS analog-design reuse," IEEE Design Test Comput., pp. 50-58, Mar.-Apr. 2002.
3. S. Funaba, A. Kitagawa, T. Tsukada, and G. Yokomizo, "A fast and accurate method of redesigning analog subcircuits for technology scaling," Anal. Integr. Circuits Signal Process., vol. 25, pp. 299-307, 2000.
4. [Online]. Available: http://www.neolinear.com
5. A. Savio, L. Colalongo, Z. Kovács-Vajna, and M. Quarantelli, "Scaling rules and parameter tuning procedure for analog design reuse in technology migration," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'04), Vancouver, Canada, May 23-26, 2004, vol. 5, pp. V 117-V 120.
6. K. Bult, "Analog broadband communication circuits in pure digital deep sub-micron CMOS," in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC'99), San Francisco, CA, Feb. 15-17, 1999, vol. 42, pp. 76-77.
7. H. Samueli, "Broadband communicstions ICs: Enabling high-band-width connectivity in the home and office," in Slide Suppl. IEEE Int. Solid-State Circuits Conf. (ISSCC'99), San Francisco, CA, Feb. 15-17, 1999, vol. 42, pp. 29-35.
8. W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, Numerical Recipes in C, 2nd ed. Cambridge, U.K.: Cambridge University Press, 2002.
9. A. I. A. Cunha, M. C. Schneider, and C. Galup-Montoro, "An MOS transistor model for analog circuit design," IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, Oct. 1998.
10. Star-Hspice Manual, Release 2001.2 Avant! Corporation. Austin, TX, Jun. 2001.
11. Y. P. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1987.