Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs

IEEE Transactions on Electron Devices

Volumn 52, Issue 7, 2005, Pages 1603-1609

  Kumar, D Vinay ^a   Narasimhulu, K ^a   Reddy, P S ^b   Shojaei Baghini, M ^a   Sharma, Dinesh K ^a   Patil, Mahesh B ^a   Rao, V Ramgopal ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b INTEL TECHNOLOGY INDIA PVT LTD   (India)

Author keywords

Analog circuit; Channel engineering; Lateral asymmetric channel (LAC); Look up table (LUT); MOSFET; Quasi static

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); OPERATIONAL AMPLIFIERS; PERFORMANCE; TABLE LOOKUP;

ANALOG CIRCUIT; CHANNEL ENGINEERING; LATERAL ASYMMETRIC CHANNEL (LAC);

MOSFET DEVICES;

EID: 23944498418     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.850941     Document Type: Article

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