Technologies for (sub-) 45nm analog/RF CMOS - circuit design opportunities and challenges

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 679-686

  Decoutere, S ^a   Wambacq, P ^b   Subramanian, V ^c   Borremans, J ^b   Mercha, A ^a  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL;

MATCHING PERFORMANCE; MOBILITY ENHANCEMENT;

CMOS INTEGRATED CIRCUITS;

EID: 39049101399     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320879     Document Type: Conference Paper

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